drivers/clk/sunxi/clk_a31.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 Amarula Solutions B.V.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <clk/sunxi.h>
  12 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  13 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  14 #include <linux/bitops.h>
  15
  16 static struct ccu_clk_gate a31_gates[] = {
  17         [CLK_AHB1_MMC0]         = GATE(0x060, BIT(8)),
  18         [CLK_AHB1_MMC1]         = GATE(0x060, BIT(9)),
  19         [CLK_AHB1_MMC2]         = GATE(0x060, BIT(10)),
  20         [CLK_AHB1_MMC3]         = GATE(0x060, BIT(11)),
  21         [CLK_AHB1_EMAC]         = GATE(0x060, BIT(17)),
  22         [CLK_AHB1_SPI0]         = GATE(0x060, BIT(20)),
  23         [CLK_AHB1_SPI1]         = GATE(0x060, BIT(21)),
  24         [CLK_AHB1_SPI2]         = GATE(0x060, BIT(22)),
  25         [CLK_AHB1_SPI3]         = GATE(0x060, BIT(23)),
  26         [CLK_AHB1_OTG]          = GATE(0x060, BIT(24)),
  27         [CLK_AHB1_EHCI0]        = GATE(0x060, BIT(26)),
  28         [CLK_AHB1_EHCI1]        = GATE(0x060, BIT(27)),
  29         [CLK_AHB1_OHCI0]        = GATE(0x060, BIT(29)),
  30         [CLK_AHB1_OHCI1]        = GATE(0x060, BIT(30)),
  31         [CLK_AHB1_OHCI2]        = GATE(0x060, BIT(31)),
  32
  33         [CLK_APB1_PIO]          = GATE(0x068, BIT(5)),
  34
  35         [CLK_APB2_I2C0]         = GATE(0x06c, BIT(0)),
  36         [CLK_APB2_I2C1]         = GATE(0x06c, BIT(1)),
  37         [CLK_APB2_I2C2]         = GATE(0x06c, BIT(2)),
  38         [CLK_APB2_I2C3]         = GATE(0x06c, BIT(3)),
  39         [CLK_APB2_UART0]        = GATE(0x06c, BIT(16)),
  40         [CLK_APB2_UART1]        = GATE(0x06c, BIT(17)),
  41         [CLK_APB2_UART2]        = GATE(0x06c, BIT(18)),
  42         [CLK_APB2_UART3]        = GATE(0x06c, BIT(19)),
  43         [CLK_APB2_UART4]        = GATE(0x06c, BIT(20)),
  44         [CLK_APB2_UART5]        = GATE(0x06c, BIT(21)),
  45
  46         [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
  47         [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
  48         [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
  49         [CLK_SPI3]              = GATE(0x0ac, BIT(31)),
  50
  51         [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
  52         [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
  53         [CLK_USB_PHY2]          = GATE(0x0cc, BIT(10)),
  54         [CLK_USB_OHCI0]         = GATE(0x0cc, BIT(16)),
  55         [CLK_USB_OHCI1]         = GATE(0x0cc, BIT(17)),
  56         [CLK_USB_OHCI2]         = GATE(0x0cc, BIT(18)),
  57 };
  58
  59 static struct ccu_reset a31_resets[] = {
  60         [RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
  61         [RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
  62         [RST_USB_PHY2]          = RESET(0x0cc, BIT(2)),
  63
  64         [RST_AHB1_MMC0]         = RESET(0x2c0, BIT(8)),
  65         [RST_AHB1_MMC1]         = RESET(0x2c0, BIT(9)),
  66         [RST_AHB1_MMC2]         = RESET(0x2c0, BIT(10)),
  67         [RST_AHB1_MMC3]         = RESET(0x2c0, BIT(11)),
  68         [RST_AHB1_EMAC]         = RESET(0x2c0, BIT(17)),
  69         [RST_AHB1_SPI0]         = RESET(0x2c0, BIT(20)),
  70         [RST_AHB1_SPI1]         = RESET(0x2c0, BIT(21)),
  71         [RST_AHB1_SPI2]         = RESET(0x2c0, BIT(22)),
  72         [RST_AHB1_SPI3]         = RESET(0x2c0, BIT(23)),
  73         [RST_AHB1_OTG]          = RESET(0x2c0, BIT(24)),
  74         [RST_AHB1_EHCI0]        = RESET(0x2c0, BIT(26)),
  75         [RST_AHB1_EHCI1]        = RESET(0x2c0, BIT(27)),
  76         [RST_AHB1_OHCI0]        = RESET(0x2c0, BIT(29)),
  77         [RST_AHB1_OHCI1]        = RESET(0x2c0, BIT(30)),
  78         [RST_AHB1_OHCI2]        = RESET(0x2c0, BIT(31)),
  79
  80         [RST_APB2_I2C0]         = RESET(0x2d8, BIT(0)),
  81         [RST_APB2_I2C1]         = RESET(0x2d8, BIT(1)),
  82         [RST_APB2_I2C2]         = RESET(0x2d8, BIT(2)),
  83         [RST_APB2_I2C3]         = RESET(0x2d8, BIT(3)),
  84         [RST_APB2_UART0]        = RESET(0x2d8, BIT(16)),
  85         [RST_APB2_UART1]        = RESET(0x2d8, BIT(17)),
  86         [RST_APB2_UART2]        = RESET(0x2d8, BIT(18)),
  87         [RST_APB2_UART3]        = RESET(0x2d8, BIT(19)),
  88         [RST_APB2_UART4]        = RESET(0x2d8, BIT(20)),
  89         [RST_APB2_UART5]        = RESET(0x2d8, BIT(21)),
  90 };
  91
  92 static const struct ccu_desc a31_ccu_desc = {
  93         .gates = a31_gates,
  94         .resets = a31_resets,
  95 };
  96
  97 static int a31_clk_bind(struct udevice *dev)
  98 {
  99         return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
 100 }
 101
 102 static const struct udevice_id a31_clk_ids[] = {
 103         { .compatible = "allwinner,sun6i-a31-ccu",
 104           .data = (ulong)&a31_ccu_desc },
 105         { }
 106 };
 107
 108 U_BOOT_DRIVER(clk_sun6i_a31) = {
 109         .name           = "sun6i_a31_ccu",
 110         .id             = UCLASS_CLK,
 111         .of_match       = a31_clk_ids,
 112         .priv_auto      = sizeof(struct ccu_priv),
 113         .ops            = &sunxi_clk_ops,
 114         .probe          = sunxi_clk_probe,
 115         .bind           = a31_clk_bind,
 116 };