drivers/clk/renesas/r8a7796-cpg-mssr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Renesas R8A7796 CPG MSSR driver
   4  *
   5  * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Based on the following driver from Linux kernel:
   8  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
   9  *
  10  * Copyright (C) 2016 Glider bvba
  11  */
  12
  13 #include <common.h>
  14 #include <clk-uclass.h>
  15 #include <dm.h>
  16
  17 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
  18
  19 #include "renesas-cpg-mssr.h"
  20 #include "rcar-gen3-cpg.h"
  21
  22 enum clk_ids {
  23         /* Core Clock Outputs exported to DT */
  24         LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
  25
  26         /* External Input Clocks */
  27         CLK_EXTAL,
  28         CLK_EXTALR,
  29
  30         /* Internal Core Clocks */
  31         CLK_MAIN,
  32         CLK_PLL0,
  33         CLK_PLL1,
  34         CLK_PLL2,
  35         CLK_PLL3,
  36         CLK_PLL4,
  37         CLK_PLL1_DIV2,
  38         CLK_PLL1_DIV4,
  39         CLK_S0,
  40         CLK_S1,
  41         CLK_S2,
  42         CLK_S3,
  43         CLK_SDSRC,
  44         CLK_RPCSRC,
  45         CLK_SSPSRC,
  46         CLK_RINT,
  47
  48         /* Module Clocks */
  49         MOD_CLK_BASE
  50 };
  51
  52 static const struct cpg_core_clk r8a7796_core_clks[] = {
  53         /* External Clock Inputs */
  54         DEF_INPUT("extal",      CLK_EXTAL),
  55         DEF_INPUT("extalr",     CLK_EXTALR),
  56
  57         /* Internal Core Clocks */
  58         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  59         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  60         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  61         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
  62         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  63         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
  64
  65         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
  66         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
  67         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
  68         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
  69         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
  70         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
  71         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
  72         DEF_FIXED(".rpcsrc",    CLK_RPCSRC,        CLK_PLL1,       2, 1),
  73
  74         /* Core Clock Outputs */
  75         DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
  76         DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  77         DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
  78         DEF_FIXED("zx",         R8A7796_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
  79         DEF_FIXED("s0d1",       R8A7796_CLK_S0D1,  CLK_S0,         1, 1),
  80         DEF_FIXED("s0d2",       R8A7796_CLK_S0D2,  CLK_S0,         2, 1),
  81         DEF_FIXED("s0d3",       R8A7796_CLK_S0D3,  CLK_S0,         3, 1),
  82         DEF_FIXED("s0d4",       R8A7796_CLK_S0D4,  CLK_S0,         4, 1),
  83         DEF_FIXED("s0d6",       R8A7796_CLK_S0D6,  CLK_S0,         6, 1),
  84         DEF_FIXED("s0d8",       R8A7796_CLK_S0D8,  CLK_S0,         8, 1),
  85         DEF_FIXED("s0d12",      R8A7796_CLK_S0D12, CLK_S0,        12, 1),
  86         DEF_FIXED("s1d1",       R8A7796_CLK_S1D1,  CLK_S1,         1, 1),
  87         DEF_FIXED("s1d2",       R8A7796_CLK_S1D2,  CLK_S1,         2, 1),
  88         DEF_FIXED("s1d4",       R8A7796_CLK_S1D4,  CLK_S1,         4, 1),
  89         DEF_FIXED("s2d1",       R8A7796_CLK_S2D1,  CLK_S2,         1, 1),
  90         DEF_FIXED("s2d2",       R8A7796_CLK_S2D2,  CLK_S2,         2, 1),
  91         DEF_FIXED("s2d4",       R8A7796_CLK_S2D4,  CLK_S2,         4, 1),
  92         DEF_FIXED("s3d1",       R8A7796_CLK_S3D1,  CLK_S3,         1, 1),
  93         DEF_FIXED("s3d2",       R8A7796_CLK_S3D2,  CLK_S3,         2, 1),
  94         DEF_FIXED("s3d4",       R8A7796_CLK_S3D4,  CLK_S3,         4, 1),
  95
  96         DEF_GEN3_SD("sd0",      R8A7796_CLK_SD0,   CLK_SDSRC,     0x074),
  97         DEF_GEN3_SD("sd1",      R8A7796_CLK_SD1,   CLK_SDSRC,     0x078),
  98         DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,     0x268),
  99         DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,     0x26c),
 100
 101         DEF_GEN3_RPC("rpc",     R8A7796_CLK_RPC,   CLK_RPCSRC,    0x238),
 102
 103         DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 104         DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),
 105
 106         /* NOTE: HDMI, CSI, CAN etc. clock are missing */
 107
 108         DEF_BASE("r",           R8A7796_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 109 };
 110
 111 static const struct mssr_mod_clk r8a7796_mod_clks[] = {
 112         DEF_MOD("scif5",                 202,   R8A7796_CLK_S3D4),
 113         DEF_MOD("scif4",                 203,   R8A7796_CLK_S3D4),
 114         DEF_MOD("scif3",                 204,   R8A7796_CLK_S3D4),
 115         DEF_MOD("scif1",                 206,   R8A7796_CLK_S3D4),
 116         DEF_MOD("scif0",                 207,   R8A7796_CLK_S3D4),
 117         DEF_MOD("msiof3",                208,   R8A7796_CLK_MSO),
 118         DEF_MOD("msiof2",                209,   R8A7796_CLK_MSO),
 119         DEF_MOD("msiof1",                210,   R8A7796_CLK_MSO),
 120         DEF_MOD("msiof0",                211,   R8A7796_CLK_MSO),
 121         DEF_MOD("sys-dmac2",             217,   R8A7796_CLK_S0D3),
 122         DEF_MOD("sys-dmac1",             218,   R8A7796_CLK_S0D3),
 123         DEF_MOD("sys-dmac0",             219,   R8A7796_CLK_S0D3),
 124         DEF_MOD("cmt3",                  300,   R8A7796_CLK_R),
 125         DEF_MOD("cmt2",                  301,   R8A7796_CLK_R),
 126         DEF_MOD("cmt1",                  302,   R8A7796_CLK_R),
 127         DEF_MOD("cmt0",                  303,   R8A7796_CLK_R),
 128         DEF_MOD("scif2",                 310,   R8A7796_CLK_S3D4),
 129         DEF_MOD("sdif3",                 311,   R8A7796_CLK_SD3),
 130         DEF_MOD("sdif2",                 312,   R8A7796_CLK_SD2),
 131         DEF_MOD("sdif1",                 313,   R8A7796_CLK_SD1),
 132         DEF_MOD("sdif0",                 314,   R8A7796_CLK_SD0),
 133         DEF_MOD("pcie1",                 318,   R8A7796_CLK_S3D1),
 134         DEF_MOD("pcie0",                 319,   R8A7796_CLK_S3D1),
 135         DEF_MOD("usb3-if0",              328,   R8A7796_CLK_S3D1),
 136         DEF_MOD("usb-dmac0",             330,   R8A7796_CLK_S3D1),
 137         DEF_MOD("usb-dmac1",             331,   R8A7796_CLK_S3D1),
 138         DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),
 139         DEF_MOD("intc-ex",               407,   R8A7796_CLK_CP),
 140         DEF_MOD("intc-ap",               408,   R8A7796_CLK_S3D1),
 141         DEF_MOD("audmac1",               501,   R8A7796_CLK_S0D3),
 142         DEF_MOD("audmac0",               502,   R8A7796_CLK_S0D3),
 143         DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),
 144         DEF_MOD("drif6",                 509,   R8A7796_CLK_S3D2),
 145         DEF_MOD("drif5",                 510,   R8A7796_CLK_S3D2),
 146         DEF_MOD("drif4",                 511,   R8A7796_CLK_S3D2),
 147         DEF_MOD("drif3",                 512,   R8A7796_CLK_S3D2),
 148         DEF_MOD("drif2",                 513,   R8A7796_CLK_S3D2),
 149         DEF_MOD("drif1",                 514,   R8A7796_CLK_S3D2),
 150         DEF_MOD("drif0",                 515,   R8A7796_CLK_S3D2),
 151         DEF_MOD("hscif4",                516,   R8A7796_CLK_S3D1),
 152         DEF_MOD("hscif3",                517,   R8A7796_CLK_S3D1),
 153         DEF_MOD("hscif2",                518,   R8A7796_CLK_S3D1),
 154         DEF_MOD("hscif1",                519,   R8A7796_CLK_S3D1),
 155         DEF_MOD("hscif0",                520,   R8A7796_CLK_S3D1),
 156         DEF_MOD("thermal",               522,   R8A7796_CLK_CP),
 157         DEF_MOD("pwm",                   523,   R8A7796_CLK_S0D12),
 158         DEF_MOD("fcpvd2",                601,   R8A7796_CLK_S0D2),
 159         DEF_MOD("fcpvd1",                602,   R8A7796_CLK_S0D2),
 160         DEF_MOD("fcpvd0",                603,   R8A7796_CLK_S0D2),
 161         DEF_MOD("fcpvb0",                607,   R8A7796_CLK_S0D1),
 162         DEF_MOD("fcpvi0",                611,   R8A7796_CLK_S0D1),
 163         DEF_MOD("fcpf0",                 615,   R8A7796_CLK_S0D1),
 164         DEF_MOD("fcpci0",                617,   R8A7796_CLK_S0D2),
 165         DEF_MOD("fcpcs",                 619,   R8A7796_CLK_S0D2),
 166         DEF_MOD("vspd2",                 621,   R8A7796_CLK_S0D2),
 167         DEF_MOD("vspd1",                 622,   R8A7796_CLK_S0D2),
 168         DEF_MOD("vspd0",                 623,   R8A7796_CLK_S0D2),
 169         DEF_MOD("vspb",                  626,   R8A7796_CLK_S0D1),
 170         DEF_MOD("vspi0",                 631,   R8A7796_CLK_S0D1),
 171         DEF_MOD("ehci1",                 702,   R8A7796_CLK_S3D4),
 172         DEF_MOD("ehci0",                 703,   R8A7796_CLK_S3D4),
 173         DEF_MOD("hsusb",                 704,   R8A7796_CLK_S3D4),
 174         DEF_MOD("csi20",                 714,   R8A7796_CLK_CSI0),
 175         DEF_MOD("csi40",                 716,   R8A7796_CLK_CSI0),
 176         DEF_MOD("du2",                   722,   R8A7796_CLK_S2D1),
 177         DEF_MOD("du1",                   723,   R8A7796_CLK_S2D1),
 178         DEF_MOD("du0",                   724,   R8A7796_CLK_S2D1),
 179         DEF_MOD("lvds",                  727,   R8A7796_CLK_S2D1),
 180         DEF_MOD("hdmi0",                 729,   R8A7796_CLK_HDMI),
 181         DEF_MOD("vin7",                  804,   R8A7796_CLK_S0D2),
 182         DEF_MOD("vin6",                  805,   R8A7796_CLK_S0D2),
 183         DEF_MOD("vin5",                  806,   R8A7796_CLK_S0D2),
 184         DEF_MOD("vin4",                  807,   R8A7796_CLK_S0D2),
 185         DEF_MOD("vin3",                  808,   R8A7796_CLK_S0D2),
 186         DEF_MOD("vin2",                  809,   R8A7796_CLK_S0D2),
 187         DEF_MOD("vin1",                  810,   R8A7796_CLK_S0D2),
 188         DEF_MOD("vin0",                  811,   R8A7796_CLK_S0D2),
 189         DEF_MOD("etheravb",              812,   R8A7796_CLK_S0D6),
 190         DEF_MOD("imr1",                  822,   R8A7796_CLK_S0D2),
 191         DEF_MOD("imr0",                  823,   R8A7796_CLK_S0D2),
 192         DEF_MOD("gpio7",                 905,   R8A7796_CLK_S3D4),
 193         DEF_MOD("gpio6",                 906,   R8A7796_CLK_S3D4),
 194         DEF_MOD("gpio5",                 907,   R8A7796_CLK_S3D4),
 195         DEF_MOD("gpio4",                 908,   R8A7796_CLK_S3D4),
 196         DEF_MOD("gpio3",                 909,   R8A7796_CLK_S3D4),
 197         DEF_MOD("gpio2",                 910,   R8A7796_CLK_S3D4),
 198         DEF_MOD("gpio1",                 911,   R8A7796_CLK_S3D4),
 199         DEF_MOD("gpio0",                 912,   R8A7796_CLK_S3D4),
 200         DEF_MOD("can-fd",                914,   R8A7796_CLK_S3D2),
 201         DEF_MOD("can-if1",               915,   R8A7796_CLK_S3D4),
 202         DEF_MOD("can-if0",               916,   R8A7796_CLK_S3D4),
 203         DEF_MOD("rpc",                   917,   R8A7796_CLK_RPC),
 204         DEF_MOD("i2c6",                  918,   R8A7796_CLK_S0D6),
 205         DEF_MOD("i2c5",                  919,   R8A7796_CLK_S0D6),
 206         DEF_MOD("i2c-dvfs",              926,   R8A7796_CLK_CP),
 207         DEF_MOD("i2c4",                  927,   R8A7796_CLK_S0D6),
 208         DEF_MOD("i2c3",                  928,   R8A7796_CLK_S0D6),
 209         DEF_MOD("i2c2",                  929,   R8A7796_CLK_S3D2),
 210         DEF_MOD("i2c1",                  930,   R8A7796_CLK_S3D2),
 211         DEF_MOD("i2c0",                  931,   R8A7796_CLK_S3D2),
 212         DEF_MOD("ssi-all",              1005,   R8A7796_CLK_S3D4),
 213         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 214         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 215         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 216         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 217         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 218         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 219         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 220         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 221         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 222         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 223         DEF_MOD("scu-all",              1017,   R8A7796_CLK_S3D4),
 224         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 225         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 226         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 227         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 228         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 229         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 230         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 231         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 232         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 233         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 234         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 235         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 236         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 237         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 238 };
 239
 240 /*
 241  * CPG Clock Data
 242  */
 243
 244 /*
 245  *   MD         EXTAL           PLL0    PLL1    PLL2    PLL3    PLL4
 246  * 14 13 19 17  (MHz)
 247  *-------------------------------------------------------------------
 248  * 0  0  0  0   16.66 x 1       x180    x192    x144    x192    x144
 249  * 0  0  0  1   16.66 x 1       x180    x192    x144    x128    x144
 250  * 0  0  1  0   Prohibited setting
 251  * 0  0  1  1   16.66 x 1       x180    x192    x144    x192    x144
 252  * 0  1  0  0   20    x 1       x150    x160    x120    x160    x120
 253  * 0  1  0  1   20    x 1       x150    x160    x120    x106    x120
 254  * 0  1  1  0   Prohibited setting
 255  * 0  1  1  1   20    x 1       x150    x160    x120    x160    x120
 256  * 1  0  0  0   25    x 1       x120    x128    x96     x128    x96
 257  * 1  0  0  1   25    x 1       x120    x128    x96     x84     x96
 258  * 1  0  1  0   Prohibited setting
 259  * 1  0  1  1   25    x 1       x120    x128    x96     x128    x96
 260  * 1  1  0  0   33.33 / 2       x180    x192    x144    x192    x144
 261  * 1  1  0  1   33.33 / 2       x180    x192    x144    x128    x144
 262  * 1  1  1  0   Prohibited setting
 263  * 1  1  1  1   33.33 / 2       x180    x192    x144    x192    x144
 264  */
 265 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 11) | \
 266                                          (((md) & BIT(13)) >> 11) | \
 267                                          (((md) & BIT(19)) >> 18) | \
 268                                          (((md) & BIT(17)) >> 17))
 269
 270 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
 271         /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
 272         { 1,            192,    1,      192,    1,      },
 273         { 1,            192,    1,      128,    1,      },
 274         { 0, /* Prohibited setting */                   },
 275         { 1,            192,    1,      192,    1,      },
 276         { 1,            160,    1,      160,    1,      },
 277         { 1,            160,    1,      106,    1,      },
 278         { 0, /* Prohibited setting */                   },
 279         { 1,            160,    1,      160,    1,      },
 280         { 1,            128,    1,      128,    1,      },
 281         { 1,            128,    1,      84,     1,      },
 282         { 0, /* Prohibited setting */                   },
 283         { 1,            128,    1,      128,    1,      },
 284         { 2,            192,    1,      192,    1,      },
 285         { 2,            192,    1,      128,    1,      },
 286         { 0, /* Prohibited setting */                   },
 287         { 2,            192,    1,      192,    1,      },
 288 };
 289
 290 static const struct mstp_stop_table r8a7796_mstp_table[] = {
 291         { 0x00200000, 0x0, 0x00200000, 0 },
 292         { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
 293         { 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
 294         { 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
 295         { 0x80000184, 0x180, 0x80000184, 0 },
 296         { 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
 297         { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
 298         { 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
 299         { 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
 300         { 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
 301         { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
 302         { 0x000000B7, 0x0, 0x000000B7, 0 },
 303 };
 304
 305 static const void *r8a7796_get_pll_config(const u32 cpg_mode)
 306 {
 307         return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 308 }
 309
 310 static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
 311         .core_clk               = r8a7796_core_clks,
 312         .core_clk_size          = ARRAY_SIZE(r8a7796_core_clks),
 313         .mod_clk                = r8a7796_mod_clks,
 314         .mod_clk_size           = ARRAY_SIZE(r8a7796_mod_clks),
 315         .mstp_table             = r8a7796_mstp_table,
 316         .mstp_table_size        = ARRAY_SIZE(r8a7796_mstp_table),
 317         .reset_node             = "renesas,r8a7796-rst",
 318         .extalr_node            = "extalr",
 319         .mod_clk_base           = MOD_CLK_BASE,
 320         .clk_extal_id           = CLK_EXTAL,
 321         .clk_extalr_id          = CLK_EXTALR,
 322         .get_pll_config         = r8a7796_get_pll_config,
 323 };
 324
 325 static const struct cpg_mssr_info r8a77965_cpg_mssr_info = {
 326         .core_clk               = r8a7796_core_clks,
 327         .core_clk_size          = ARRAY_SIZE(r8a7796_core_clks),
 328         .mod_clk                = r8a7796_mod_clks,
 329         .mod_clk_size           = ARRAY_SIZE(r8a7796_mod_clks),
 330         .mstp_table             = r8a7796_mstp_table,
 331         .mstp_table_size        = ARRAY_SIZE(r8a7796_mstp_table),
 332         .reset_node             = "renesas,r8a77965-rst",
 333         .extalr_node            = "extalr",
 334         .mod_clk_base           = MOD_CLK_BASE,
 335         .clk_extal_id           = CLK_EXTAL,
 336         .clk_extalr_id          = CLK_EXTALR,
 337         .get_pll_config         = r8a7796_get_pll_config,
 338 };
 339
 340 static const struct udevice_id r8a7796_clk_ids[] = {
 341         {
 342                 .compatible     = "renesas,r8a7796-cpg-mssr",
 343                 .data           = (ulong)&r8a7796_cpg_mssr_info,
 344         },
 345         {
 346                 .compatible     = "renesas,r8a77965-cpg-mssr",
 347                 .data           = (ulong)&r8a77965_cpg_mssr_info,
 348         },
 349         { }
 350 };
 351
 352 U_BOOT_DRIVER(clk_r8a7796) = {
 353         .name           = "clk_r8a7796",
 354         .id             = UCLASS_CLK,
 355         .of_match       = r8a7796_clk_ids,
 356         .priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
 357         .ops            = &gen3_clk_ops,
 358         .probe          = gen3_clk_probe,
 359         .remove         = gen3_clk_remove,
 360 };