1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Gated clock implementation
13 #include <clk-uclass.h>
14 #include <dm/device.h>
15 #include <dm/devres.h>
16 #include <linux/bitops.h>
17 #include <linux/clk-provider.h>
20 #include <linux/err.h>
22 #define UBOOT_DM_CLK_GATE "clk_gate"
25 * DOC: basic gatable clock which can gate and ungate it's output
27 * Traits of this clock:
28 * prepare - clk_(un)prepare only ensures parent is (un)prepared
29 * enable - clk_enable and clk_disable are functional & control gating
30 * rate - inherits rate from parent. No clk_set_rate support
31 * parent - fixed parent. No clk_set_parent support
35 * It works on following logic:
37 * For enabling clock, enable = 1
38 * set2dis = 1 -> clear bit -> set = 0
39 * set2dis = 0 -> set bit -> set = 1
41 * For disabling clock, enable = 0
42 * set2dis = 1 -> set bit -> set = 1
43 * set2dis = 0 -> clear bit -> set = 0
45 * So, result is always: enable xor set2dis.
47 static void clk_gate_endisable(struct clk *clk, int enable)
49 struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
50 dev_get_clk_ptr(clk->dev) : clk);
51 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
56 if (gate->flags & CLK_GATE_HIWORD_MASK) {
57 reg = BIT(gate->bit_idx + 16);
59 reg |= BIT(gate->bit_idx);
61 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
62 reg = gate->io_gate_val;
64 reg = readl(gate->reg);
68 reg |= BIT(gate->bit_idx);
70 reg &= ~BIT(gate->bit_idx);
73 writel(reg, gate->reg);
76 static int clk_gate_enable(struct clk *clk)
78 clk_gate_endisable(clk, 1);
83 static int clk_gate_disable(struct clk *clk)
85 clk_gate_endisable(clk, 0);
90 int clk_gate_is_enabled(struct clk *clk)
92 struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
93 dev_get_clk_ptr(clk->dev) : clk);
96 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
97 reg = gate->io_gate_val;
99 reg = readl(gate->reg);
102 /* if a set bit disables this clk, flip it before masking */
103 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
104 reg ^= BIT(gate->bit_idx);
106 reg &= BIT(gate->bit_idx);
111 const struct clk_ops clk_gate_ops = {
112 .enable = clk_gate_enable,
113 .disable = clk_gate_disable,
114 .get_rate = clk_generic_get_rate,
117 struct clk *clk_register_gate(struct device *dev, const char *name,
118 const char *parent_name, unsigned long flags,
119 void __iomem *reg, u8 bit_idx,
120 u8 clk_gate_flags, spinlock_t *lock)
122 struct clk_gate *gate;
126 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
128 pr_err("gate bit exceeds LOWORD field\n");
129 return ERR_PTR(-EINVAL);
133 /* allocate the gate */
134 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
136 return ERR_PTR(-ENOMEM);
138 /* struct clk_gate assignments */
140 gate->bit_idx = bit_idx;
141 gate->flags = clk_gate_flags;
142 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
143 gate->io_gate_val = *(u32 *)reg;
148 ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
157 U_BOOT_DRIVER(clk_gate) = {
158 .name = UBOOT_DM_CLK_GATE,
160 .ops = &clk_gate_ops,
161 .flags = DM_FLAG_PRE_RELOC,