1 // SPDX-License-Identifier: GPL-2.0+
3 * Compatible code for non CCF AT91 platforms.
5 * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
7 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
10 #include <clk-uclass.h>
12 #include <asm/global_data.h>
13 #include <dm/device_compat.h>
16 #include <mach/at91_pmc.h>
17 #include <mach/at91_sfr.h>
23 DECLARE_GLOBAL_DATA_PTR;
26 struct at91_pmc *reg_base;
27 struct regmap *regmap_sfr;
30 static const struct udevice_id at91_pmc_match[] = {
31 { .compatible = "atmel,at91rm9200-pmc" },
32 { .compatible = "atmel,at91sam9260-pmc" },
33 { .compatible = "atmel,at91sam9g45-pmc" },
34 { .compatible = "atmel,at91sam9n12-pmc" },
35 { .compatible = "atmel,at91sam9x5-pmc" },
36 { .compatible = "atmel,sama5d3-pmc" },
37 { .compatible = "atmel,sama5d2-pmc" },
41 U_BOOT_DRIVER(at91_pmc) = {
43 .id = UCLASS_SIMPLE_BUS,
44 .of_match = at91_pmc_match,
47 static int at91_pmc_core_probe(struct udevice *dev)
49 struct pmc_plat *plat = dev_get_plat(dev);
51 dev = dev_get_parent(dev);
53 plat->reg_base = dev_read_addr_ptr(dev);
59 * at91_clk_sub_device_bind() - for the at91 clock driver
60 * Recursively bind its children as clk devices.
62 * @return: 0 on success, or negative error code on failure
64 int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
66 const void *fdt = gd->fdt_blob;
67 int offset = dev_of_offset(dev);
68 bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
72 for (offset = fdt_first_subnode(fdt, offset);
74 offset = fdt_next_subnode(fdt, offset)) {
76 !ofnode_pre_reloc(offset_to_ofnode(offset)))
79 * If this node has "compatible" property, this is not
80 * a clock sub-node, but a normal device. skip.
82 fdt_get_property(fdt, offset, "compatible", &ret);
86 if (ret != -FDT_ERR_NOTFOUND)
89 name = fdt_get_name(fdt, offset, NULL);
92 ret = device_bind_driver_to_node(dev, drv_name, name,
93 offset_to_ofnode(offset), NULL);
101 int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
105 if (args->args_count) {
106 debug("Invalid args_count: %d\n", args->args_count);
110 periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
120 int at91_clk_probe(struct udevice *dev)
122 struct udevice *dev_periph_container, *dev_pmc;
123 struct pmc_plat *plat = dev_get_plat(dev);
125 dev_periph_container = dev_get_parent(dev);
126 dev_pmc = dev_get_parent(dev_periph_container);
128 plat->reg_base = dev_read_addr_ptr(dev_pmc);
133 /* SCKC specific code. */
134 static const struct udevice_id at91_sckc_match[] = {
135 { .compatible = "atmel,at91sam9x5-sckc" },
139 U_BOOT_DRIVER(at91_sckc) = {
141 .id = UCLASS_SIMPLE_BUS,
142 .of_match = at91_sckc_match,
145 /* Slow clock specific code. */
146 static int at91_slow_clk_enable(struct clk *clk)
151 static ulong at91_slow_clk_get_rate(struct clk *clk)
153 return CONFIG_SYS_AT91_SLOW_CLOCK;
156 static struct clk_ops at91_slow_clk_ops = {
157 .enable = at91_slow_clk_enable,
158 .get_rate = at91_slow_clk_get_rate,
161 static const struct udevice_id at91_slow_clk_match[] = {
162 { .compatible = "atmel,at91sam9x5-clk-slow" },
166 U_BOOT_DRIVER(at91_slow_clk) = {
167 .name = "at91-slow-clk",
169 .of_match = at91_slow_clk_match,
170 .ops = &at91_slow_clk_ops,
173 /* Master clock specific code. */
174 static ulong at91_master_clk_get_rate(struct clk *clk)
176 return gd->arch.mck_rate_hz;
179 static struct clk_ops at91_master_clk_ops = {
180 .get_rate = at91_master_clk_get_rate,
183 static const struct udevice_id at91_master_clk_match[] = {
184 { .compatible = "atmel,at91rm9200-clk-master" },
185 { .compatible = "atmel,at91sam9x5-clk-master" },
189 U_BOOT_DRIVER(at91_master_clk) = {
190 .name = "at91-master-clk",
192 .of_match = at91_master_clk_match,
193 .ops = &at91_master_clk_ops,
196 /* Main osc clock specific code. */
197 static int main_osc_clk_enable(struct clk *clk)
199 struct pmc_plat *plat = dev_get_plat(clk->dev);
200 struct at91_pmc *pmc = plat->reg_base;
202 if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
208 static ulong main_osc_clk_get_rate(struct clk *clk)
210 return gd->arch.main_clk_rate_hz;
213 static struct clk_ops main_osc_clk_ops = {
214 .enable = main_osc_clk_enable,
215 .get_rate = main_osc_clk_get_rate,
218 static int main_osc_clk_probe(struct udevice *dev)
220 return at91_pmc_core_probe(dev);
223 static const struct udevice_id main_osc_clk_match[] = {
224 { .compatible = "atmel,at91sam9x5-clk-main" },
228 U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
229 .name = "at91sam9x5-main-osc-clk",
231 .of_match = main_osc_clk_match,
232 .probe = main_osc_clk_probe,
233 .plat_auto = sizeof(struct pmc_plat),
234 .ops = &main_osc_clk_ops,
237 /* PLLA clock specific code. */
238 static int plla_clk_enable(struct clk *clk)
240 struct pmc_plat *plat = dev_get_plat(clk->dev);
241 struct at91_pmc *pmc = plat->reg_base;
243 if (readl(&pmc->sr) & AT91_PMC_LOCKA)
249 static ulong plla_clk_get_rate(struct clk *clk)
251 return gd->arch.plla_rate_hz;
254 static struct clk_ops plla_clk_ops = {
255 .enable = plla_clk_enable,
256 .get_rate = plla_clk_get_rate,
259 static int plla_clk_probe(struct udevice *dev)
261 return at91_pmc_core_probe(dev);
264 static const struct udevice_id plla_clk_match[] = {
265 { .compatible = "atmel,sama5d3-clk-pll" },
269 U_BOOT_DRIVER(at91_plla_clk) = {
270 .name = "at91-plla-clk",
272 .of_match = plla_clk_match,
273 .probe = plla_clk_probe,
274 .plat_auto = sizeof(struct pmc_plat),
275 .ops = &plla_clk_ops,
278 /* PLLA DIV clock specific code. */
279 static int at91_plladiv_clk_enable(struct clk *clk)
284 static ulong at91_plladiv_clk_get_rate(struct clk *clk)
286 struct pmc_plat *plat = dev_get_plat(clk->dev);
287 struct at91_pmc *pmc = plat->reg_base;
292 ret = clk_get_by_index(clk->dev, 0, &source);
296 clk_rate = clk_get_rate(&source);
297 if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
303 static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
305 struct pmc_plat *plat = dev_get_plat(clk->dev);
306 struct at91_pmc *pmc = plat->reg_base;
311 ret = clk_get_by_index(clk->dev, 0, &source);
315 parent_rate = clk_get_rate(&source);
316 if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
319 if (parent_rate != rate) {
320 writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
327 static struct clk_ops at91_plladiv_clk_ops = {
328 .enable = at91_plladiv_clk_enable,
329 .get_rate = at91_plladiv_clk_get_rate,
330 .set_rate = at91_plladiv_clk_set_rate,
333 static int at91_plladiv_clk_probe(struct udevice *dev)
335 return at91_pmc_core_probe(dev);
338 static const struct udevice_id at91_plladiv_clk_match[] = {
339 { .compatible = "atmel,at91sam9x5-clk-plldiv" },
343 U_BOOT_DRIVER(at91_plladiv_clk) = {
344 .name = "at91-plladiv-clk",
346 .of_match = at91_plladiv_clk_match,
347 .probe = at91_plladiv_clk_probe,
348 .plat_auto = sizeof(struct pmc_plat),
349 .ops = &at91_plladiv_clk_ops,
352 /* System clock specific code. */
353 #define SYSTEM_MAX_ID 31
356 * at91_system_clk_bind() - for the system clock driver
357 * Recursively bind its children as clk devices.
359 * @return: 0 on success, or negative error code on failure
361 static int at91_system_clk_bind(struct udevice *dev)
363 return at91_clk_sub_device_bind(dev, "system-clk");
366 static const struct udevice_id at91_system_clk_match[] = {
367 { .compatible = "atmel,at91rm9200-clk-system" },
371 U_BOOT_DRIVER(at91_system_clk) = {
372 .name = "at91-system-clk",
374 .of_match = at91_system_clk_match,
375 .bind = at91_system_clk_bind,
378 static inline int is_pck(int id)
380 return (id >= 8) && (id <= 15);
383 static ulong system_clk_get_rate(struct clk *clk)
388 ret = clk_get_by_index(clk->dev, 0, &clk_dev);
392 return clk_get_rate(&clk_dev);
395 static ulong system_clk_set_rate(struct clk *clk, ulong rate)
400 ret = clk_get_by_index(clk->dev, 0, &clk_dev);
404 return clk_set_rate(&clk_dev, rate);
407 static int system_clk_enable(struct clk *clk)
409 struct pmc_plat *plat = dev_get_plat(clk->dev);
410 struct at91_pmc *pmc = plat->reg_base;
413 if (clk->id > SYSTEM_MAX_ID)
418 writel(mask, &pmc->scer);
421 * For the programmable clocks the Ready status in the PMC
422 * status register should be checked after enabling.
423 * For other clocks this is unnecessary.
425 if (!is_pck(clk->id))
428 while (!(readl(&pmc->sr) & mask))
434 static struct clk_ops system_clk_ops = {
435 .of_xlate = at91_clk_of_xlate,
436 .get_rate = system_clk_get_rate,
437 .set_rate = system_clk_set_rate,
438 .enable = system_clk_enable,
441 U_BOOT_DRIVER(system_clk) = {
442 .name = "system-clk",
444 .probe = at91_clk_probe,
445 .plat_auto = sizeof(struct pmc_plat),
446 .ops = &system_clk_ops,
449 /* Peripheral clock specific code. */
450 #define PERIPHERAL_ID_MIN 2
451 #define PERIPHERAL_ID_MAX 31
452 #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
454 enum periph_clk_type {
455 CLK_PERIPH_AT91RM9200 = 0,
456 CLK_PERIPH_AT91SAM9X5,
460 * sam9x5_periph_clk_bind() - for the periph clock driver
461 * Recursively bind its children as clk devices.
463 * @return: 0 on success, or negative error code on failure
465 static int sam9x5_periph_clk_bind(struct udevice *dev)
467 return at91_clk_sub_device_bind(dev, "periph-clk");
470 static const struct udevice_id sam9x5_periph_clk_match[] = {
472 .compatible = "atmel,at91rm9200-clk-peripheral",
473 .data = CLK_PERIPH_AT91RM9200,
476 .compatible = "atmel,at91sam9x5-clk-peripheral",
477 .data = CLK_PERIPH_AT91SAM9X5,
482 U_BOOT_DRIVER(sam9x5_periph_clk) = {
483 .name = "sam9x5-periph-clk",
485 .of_match = sam9x5_periph_clk_match,
486 .bind = sam9x5_periph_clk_bind,
489 static int periph_clk_enable(struct clk *clk)
491 struct pmc_plat *plat = dev_get_plat(clk->dev);
492 struct at91_pmc *pmc = plat->reg_base;
493 enum periph_clk_type clk_type;
496 if (clk->id < PERIPHERAL_ID_MIN)
499 clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
500 if (clk_type == CLK_PERIPH_AT91RM9200) {
502 if (clk->id > PERIPHERAL_ID_MAX)
505 setbits_le32(addr, PERIPHERAL_MASK(clk->id));
507 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
508 setbits_le32(&pmc->pcr,
509 AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
515 static ulong periph_get_rate(struct clk *clk)
522 dev = dev_get_parent(clk->dev);
524 ret = clk_get_by_index(dev, 0, &clk_dev);
528 clk_rate = clk_get_rate(&clk_dev);
535 static struct clk_ops periph_clk_ops = {
536 .of_xlate = at91_clk_of_xlate,
537 .enable = periph_clk_enable,
538 .get_rate = periph_get_rate,
541 U_BOOT_DRIVER(clk_periph) = {
542 .name = "periph-clk",
544 .plat_auto = sizeof(struct pmc_plat),
545 .probe = at91_clk_probe,
546 .ops = &periph_clk_ops,
549 /* UTMI clock specific code. */
550 #ifdef CONFIG_AT91_UTMI
553 * The purpose of this clock is to generate a 480 MHz signal. A different
554 * rate can't be configured.
556 #define UTMI_RATE 480000000
558 static int utmi_clk_enable(struct clk *clk)
560 struct pmc_plat *plat = dev_get_plat(clk->dev);
561 struct at91_pmc *pmc = plat->reg_base;
564 u32 utmi_ref_clk_freq;
567 int timeout = 2000000;
569 if (readl(&pmc->sr) & AT91_PMC_LOCKU)
573 * If mainck rate is different from 12 MHz, we have to configure the
574 * FREQ field of the SFR_UTMICKTRIM register to generate properly
577 err = clk_get_by_index(clk->dev, 0, &clk_dev);
581 clk_rate = clk_get_rate(&clk_dev);
584 utmi_ref_clk_freq = 0;
587 utmi_ref_clk_freq = 1;
590 utmi_ref_clk_freq = 2;
593 * Not supported on SAMA5D2 but it's not an issue since MAINCK
594 * maximum value is 24 MHz.
597 utmi_ref_clk_freq = 3;
600 printf("UTMICK: unsupported mainck rate\n");
604 if (plat->regmap_sfr) {
605 err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
609 tmp &= ~AT91_UTMICKTRIM_FREQ;
610 tmp |= utmi_ref_clk_freq;
611 err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
614 } else if (utmi_ref_clk_freq) {
615 printf("UTMICK: sfr node required\n");
619 tmp = readl(&pmc->uckr);
620 tmp |= AT91_PMC_UPLLEN |
623 writel(tmp, &pmc->uckr);
625 while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU))
628 printf("UTMICK: timeout waiting for UPLL lock\n");
635 static ulong utmi_clk_get_rate(struct clk *clk)
637 /* UTMI clk rate is fixed. */
641 static struct clk_ops utmi_clk_ops = {
642 .enable = utmi_clk_enable,
643 .get_rate = utmi_clk_get_rate,
646 static int utmi_clk_of_to_plat(struct udevice *dev)
648 struct pmc_plat *plat = dev_get_plat(dev);
649 struct udevice *syscon;
651 uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
652 "regmap-sfr", &syscon);
655 plat->regmap_sfr = syscon_get_regmap(syscon);
660 static int utmi_clk_probe(struct udevice *dev)
662 return at91_pmc_core_probe(dev);
665 static const struct udevice_id utmi_clk_match[] = {
666 { .compatible = "atmel,at91sam9x5-clk-utmi" },
670 U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
671 .name = "at91sam9x5-utmi-clk",
673 .of_match = utmi_clk_match,
674 .probe = utmi_clk_probe,
675 .of_to_plat = utmi_clk_of_to_plat,
676 .plat_auto = sizeof(struct pmc_plat),
677 .ops = &utmi_clk_ops,
680 #endif /* CONFIG_AT91_UTMI */
682 /* H32MX clock specific code. */
683 #ifdef CONFIG_AT91_H32MX
685 #define H32MX_MAX_FREQ 90000000
687 static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
689 struct pmc_plat *plat = dev_get_plat(clk->dev);
690 struct at91_pmc *pmc = plat->reg_base;
691 ulong rate = gd->arch.mck_rate_hz;
693 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
696 if (rate > H32MX_MAX_FREQ)
697 dev_dbg(clk->dev, "H32MX clock is too fast\n");
702 static struct clk_ops sama5d4_h32mx_clk_ops = {
703 .get_rate = sama5d4_h32mx_clk_get_rate,
706 static int sama5d4_h32mx_clk_probe(struct udevice *dev)
708 return at91_pmc_core_probe(dev);
711 static const struct udevice_id sama5d4_h32mx_clk_match[] = {
712 { .compatible = "atmel,sama5d4-clk-h32mx" },
716 U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
717 .name = "sama5d4-h32mx-clk",
719 .of_match = sama5d4_h32mx_clk_match,
720 .probe = sama5d4_h32mx_clk_probe,
721 .plat_auto = sizeof(struct pmc_plat),
722 .ops = &sama5d4_h32mx_clk_ops,
725 #endif /* CONFIG_AT91_H32MX */
727 /* Generic clock specific code. */
728 #ifdef CONFIG_AT91_GENERIC_CLK
730 #define GENERATED_SOURCE_MAX 6
731 #define GENERATED_MAX_DIV 255
734 * generated_clk_bind() - for the generated clock driver
735 * Recursively bind its children as clk devices.
737 * @return: 0 on success, or negative error code on failure
739 static int generated_clk_bind(struct udevice *dev)
741 return at91_clk_sub_device_bind(dev, "generic-clk");
744 static const struct udevice_id generated_clk_match[] = {
745 { .compatible = "atmel,sama5d2-clk-generated" },
749 U_BOOT_DRIVER(generated_clk) = {
750 .name = "generated-clk",
752 .of_match = generated_clk_match,
753 .bind = generated_clk_bind,
756 struct generic_clk_priv {
760 static ulong generic_clk_get_rate(struct clk *clk)
762 struct pmc_plat *plat = dev_get_plat(clk->dev);
763 struct at91_pmc *pmc = plat->reg_base;
767 u8 clock_source, parent_index;
770 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
771 tmp = readl(&pmc->pcr);
772 clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
773 AT91_PMC_PCR_GCKCSS_MASK;
774 gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
776 parent_index = clock_source - 1;
777 ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
781 clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
788 static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
790 struct pmc_plat *plat = dev_get_plat(clk->dev);
791 struct at91_pmc *pmc = plat->reg_base;
792 struct generic_clk_priv *priv = dev_get_priv(clk->dev);
793 struct clk parent, best_parent;
794 ulong tmp_rate, best_rate = rate, parent_rate;
795 int tmp_diff, best_diff = -1;
796 u32 div, best_div = 0;
797 u8 best_parent_index, best_clock_source = 0;
802 for (i = 0; i < priv->num_parents; i++) {
803 ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
807 parent_rate = clk_get_rate(&parent);
808 if (IS_ERR_VALUE(parent_rate))
811 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
812 tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
813 tmp_diff = abs(rate - tmp_rate);
815 if (best_diff < 0 || best_diff > tmp_diff) {
816 best_rate = tmp_rate;
817 best_diff = tmp_diff;
820 best_parent = parent;
821 best_parent_index = i;
822 best_clock_source = best_parent_index + 1;
825 if (!best_diff || tmp_rate < rate)
833 debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
834 best_parent.dev->name, best_rate, best_div);
836 ret = clk_enable(&best_parent);
840 writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
841 tmp = readl(&pmc->pcr);
842 tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
843 tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
844 AT91_PMC_PCR_CMD_WRITE |
845 AT91_PMC_PCR_GCKDIV_(best_div) |
847 writel(tmp, &pmc->pcr);
849 while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
855 static struct clk_ops generic_clk_ops = {
856 .of_xlate = at91_clk_of_xlate,
857 .get_rate = generic_clk_get_rate,
858 .set_rate = generic_clk_set_rate,
861 static int generic_clk_of_to_plat(struct udevice *dev)
863 struct generic_clk_priv *priv = dev_get_priv(dev);
864 u32 cells[GENERATED_SOURCE_MAX];
867 num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
868 dev_of_offset(dev_get_parent(dev)), "clocks", cells,
869 GENERATED_SOURCE_MAX);
874 priv->num_parents = num_parents;
879 U_BOOT_DRIVER(generic_clk) = {
880 .name = "generic-clk",
882 .probe = at91_clk_probe,
883 .of_to_plat = generic_clk_of_to_plat,
884 .priv_auto = sizeof(struct generic_clk_priv),
885 .plat_auto = sizeof(struct pmc_plat),
886 .ops = &generic_clk_ops,
889 #endif /* CONFIG_AT91_GENERIC_CLK */
891 /* USB clock specific code. */
892 #ifdef CONFIG_AT91_USB_CLK
894 #define AT91_USB_CLK_SOURCE_MAX 2
895 #define AT91_USB_CLK_MAX_DIV 15
897 struct at91_usb_clk_priv {
901 static ulong at91_usb_clk_get_rate(struct clk *clk)
903 struct pmc_plat *plat = dev_get_plat(clk->dev);
904 struct at91_pmc *pmc = plat->reg_base;
910 tmp = readl(&pmc->pcr);
911 source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) &
912 AT91_PMC_USB_USBS_MASK;
913 usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK;
915 ret = clk_get_by_index(clk->dev, source_index, &source);
919 return clk_get_rate(&source) / (usbdiv + 1);
922 static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
924 struct pmc_plat *plat = dev_get_plat(clk->dev);
925 struct at91_pmc *pmc = plat->reg_base;
926 struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
927 struct clk source, best_source;
928 ulong tmp_rate, best_rate = rate, source_rate;
929 int tmp_diff, best_diff = -1;
930 u32 div, best_div = 0;
931 u8 best_source_index = 0;
936 for (i = 0; i < priv->num_clksource; i++) {
937 ret = clk_get_by_index(clk->dev, i, &source);
941 source_rate = clk_get_rate(&source);
942 if (IS_ERR_VALUE(source_rate))
945 for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) {
946 tmp_rate = DIV_ROUND_CLOSEST(source_rate, div);
947 tmp_diff = abs(rate - tmp_rate);
949 if (best_diff < 0 || best_diff > tmp_diff) {
950 best_rate = tmp_rate;
951 best_diff = tmp_diff;
954 best_source = source;
955 best_source_index = i;
958 if (!best_diff || tmp_rate < rate)
966 debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n",
967 best_source.dev->name, best_rate, best_div);
969 ret = clk_enable(&best_source);
973 tmp = AT91_PMC_USB_USBS_(best_source_index) |
974 AT91_PMC_USB_DIV_(best_div);
975 writel(tmp, &pmc->usb);
980 static struct clk_ops at91_usb_clk_ops = {
981 .get_rate = at91_usb_clk_get_rate,
982 .set_rate = at91_usb_clk_set_rate,
985 static int at91_usb_clk_of_to_plat(struct udevice *dev)
987 struct at91_usb_clk_priv *priv = dev_get_priv(dev);
988 u32 cells[AT91_USB_CLK_SOURCE_MAX];
991 num_clksource = fdtdec_get_int_array_count(gd->fdt_blob,
994 AT91_USB_CLK_SOURCE_MAX);
999 priv->num_clksource = num_clksource;
1004 static int at91_usb_clk_probe(struct udevice *dev)
1006 return at91_pmc_core_probe(dev);
1009 static const struct udevice_id at91_usb_clk_match[] = {
1010 { .compatible = "atmel,at91sam9x5-clk-usb" },
1014 U_BOOT_DRIVER(at91_usb_clk) = {
1015 .name = "at91-usb-clk",
1017 .of_match = at91_usb_clk_match,
1018 .probe = at91_usb_clk_probe,
1019 .of_to_plat = at91_usb_clk_of_to_plat,
1020 .priv_auto = sizeof(struct at91_usb_clk_priv),
1021 .plat_auto = sizeof(struct pmc_plat),
1022 .ops = &at91_usb_clk_ops,
1025 #endif /* CONFIG_AT91_USB_CLK */