2 # Copyright (C) 2014, Simon Glass <sjg@chromium.org>
3 # Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
5 # SPDX-License-Identifier: GPL-2.0+
11 This document describes the information about U-Boot running on x86 targets,
12 including supported boards, build instructions, todo list, etc.
16 U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17 (Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should
18 work with minimal adjustments on other x86 boards since coreboot deals with
19 most of the low-level details.
21 U-Boot also supports booting directly from x86 reset vector, without coreboot.
22 In this case, known as bare mode, from the fact that it runs on the
23 'bare metal', U-Boot acts like a BIOS replacement. Currently Link, QEMU x86
24 targets and all Intel boards support running U-Boot 'bare metal'.
26 As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
27 Linux kernel as part of a FIT image. It also supports a compressed zImage.
28 U-Boot supports loading an x86 VxWorks kernel. Please check README.vxworks
31 Build Instructions for U-Boot as coreboot payload
32 -------------------------------------------------
33 Building U-Boot as a coreboot payload is just like building U-Boot for targets
34 on other architectures, like below:
36 $ make coreboot-x86_defconfig
39 Note this default configuration will build a U-Boot payload for the QEMU board.
40 To build a coreboot payload against another board, you can change the build
41 configuration during the 'make menuconfig' process.
45 (qemu-x86) Board configuration file
46 (qemu-x86_i440fx) Board Device Tree Source (dts) file
47 (0x01920000) Board specific Cache-As-RAM (CAR) address
48 (0x4000) Board specific Cache-As-RAM (CAR) size
50 Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
51 to point to a new board. You can also change the Cache-As-RAM (CAR) related
52 settings here if the default values do not fit your new board.
54 Build Instructions for U-Boot as BIOS replacement (bare mode)
55 -------------------------------------------------------------
56 Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
57 little bit tricky, as generally it requires several binary blobs which are not
58 shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
59 not turned on by default in the U-Boot source tree. Firstly, you need turn it
60 on by enabling the ROM build:
64 This tells the Makefile to build u-boot.rom as a target.
68 Chromebook Link specific instructions for bare mode:
70 First, you need the following binary blobs:
72 * descriptor.bin - Intel flash descriptor
73 * me.bin - Intel Management Engine
74 * mrc.bin - Memory Reference Code, which sets up SDRAM
75 * video ROM - sets up the display
77 You can get these binary blobs by:
79 $ git clone http://review.coreboot.org/p/blobs.git
82 Find the following files:
84 * ./mainboard/google/link/descriptor.bin
85 * ./mainboard/google/link/me.bin
86 * ./northbridge/intel/sandybridge/systemagent-r6.bin
88 The 3rd one should be renamed to mrc.bin.
89 As for the video ROM, you can get it here [3] and rename it to vga.bin.
90 Make sure all these binary blobs are put in the board directory.
92 Now you can build U-Boot and obtain u-boot.rom:
94 $ make chromebook_link_defconfig
99 Intel Crown Bay specific instructions for bare mode:
101 U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
102 Firmware Support Package [5] to perform all the necessary initialization steps
103 as documented in the BIOS Writer Guide, including initialization of the CPU,
104 memory controller, chipset and certain bus interfaces.
106 Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
107 install it on your host and locate the FSP binary blob. Note this platform
108 also requires a Chipset Micro Code (CMC) state machine binary to be present in
109 the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
110 in this FSP package too.
112 * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
113 * ./Microcode/C0_22211.BIN
115 Rename the first one to fsp.bin and second one to cmc.bin and put them in the
118 Note the FSP release version 001 has a bug which could cause random endless
119 loop during the FspInit call. This bug was published by Intel although Intel
120 did not describe any details. We need manually apply the patch to the FSP
121 binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
122 binary, change the following five bytes values from orginally E8 42 FF FF FF
125 As for the video ROM, you need manually extract it from the Intel provided
126 BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM
127 ID 8086:4108, extract and save it as vga.bin in the board directory.
129 Now you can build U-Boot and obtain u-boot.rom
131 $ make crownbay_defconfig
136 Intel Cougar Canyon 2 specific instructions for bare mode:
138 This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
139 with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
140 website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
141 time of writing) in the board directory and rename it to fsp.bin.
143 Now build U-Boot and obtain u-boot.rom
145 $ make cougarcanyon2_defconfig
148 The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
149 the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
150 and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
151 flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
152 this image to the SPI-0 flash according to the board manual just once and we are
153 all set. For programming U-Boot we just need to program SPI-1 flash.
157 Intel Minnowboard Max instructions for bare mode:
159 This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
160 Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
161 the time of writing). Put it in the board directory:
162 board/intel/minnowmax/fsp.bin
164 Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
165 directory: board/intel/minnowmax/vga.bin
167 You still need two more binary blobs. The first comes from the original
168 firmware image available from:
170 http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
174 $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
176 Use ifdtool in the U-Boot tools directory to extract the images from that
179 $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
181 This will provide the descriptor file - copy this into the correct place:
183 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
185 Then do the same with the sample SPI image provided in the FSP (SPI.bin at
186 the time of writing) to obtain the last image. Note that this will also
187 produce a flash descriptor file, but it does not seem to work, probably
188 because it is not designed for the Minnowmax. That is why you need to get
189 the flash descriptor from the original firmware as above.
191 $ ./tools/ifdtool -x BayleyBay/SPI.bin
192 $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
194 Now you can build U-Boot and obtain u-boot.rom
196 $ make minnowmax_defconfig
199 Checksums are as follows (but note that newer versions will invalidate this):
201 $ md5sum -b board/intel/minnowmax/*.bin
202 ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
203 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
204 894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
205 a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
207 The ROM image is broken up into these parts:
209 Offset Description Controlling config
210 ------------------------------------------------------------
211 000000 descriptor.bin Hard-coded to 0 in ifdtool
212 001000 me.bin Set by the descriptor
214 6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
215 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
216 790000 vga.bin CONFIG_VGA_BIOS_ADDR
217 7c0000 fsp.bin CONFIG_FSP_ADDR
218 7f8000 <spare> (depends on size of fsp.bin)
219 7fe000 Environment CONFIG_ENV_OFFSET
220 7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
222 Overall ROM image size is controlled by CONFIG_ROM_SIZE.
226 Intel Galileo instructions for bare mode:
228 Only one binary blob is needed for Remote Management Unit (RMU) within Intel
229 Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
230 needed by the Quark SoC itself.
232 You can get the binary blob from Quark Board Support Package from Intel website:
234 * ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
236 Rename the file and put it to the board directory by:
238 $ cp RMU.bin board/intel/galileo/rmu.bin
240 Now you can build U-Boot and obtain u-boot.rom
242 $ make galileo_defconfig
245 QEMU x86 target instructions:
247 To build u-boot.rom for QEMU x86 targets, just simply run
249 $ make qemu-x86_defconfig
252 Note this default configuration will build a U-Boot for the QEMU x86 i440FX
253 board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
254 configuration during the 'make menuconfig' process like below:
256 Device Tree Control --->
258 (qemu-x86_q35) Default Device Tree for DT control
262 For testing U-Boot as the coreboot payload, there are things that need be paid
263 attention to. coreboot supports loading an ELF executable and a 32-bit plain
264 binary, as well as other supported payloads. With the default configuration,
265 U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
266 generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
267 provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
268 this capability yet. The command is as follows:
270 # in the coreboot root directory
271 $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
272 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
274 Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
275 of _x86boot_start (in arch/x86/cpu/start.S).
277 If you want to use ELF as the coreboot payload, change U-Boot configuration to
278 use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
280 To enable video you must enable these options in coreboot:
282 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
283 - Keep VESA framebuffer
285 At present it seems that for Minnowboard Max, coreboot does not pass through
286 the video information correctly (it always says the resolution is 0x0). This
287 works correctly for link though.
289 Test with QEMU for bare mode
290 ----------------------------
291 QEMU is a fancy emulator that can enable us to test U-Boot without access to
292 a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
293 U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows:
295 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom
297 This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
298 also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
299 also supported by U-Boot. To instantiate such a machine, call QEMU with:
301 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
303 Note by default QEMU instantiated boards only have 128 MiB system memory. But
304 it is enough to have U-Boot boot and function correctly. You can increase the
305 system memory by pass '-m' parameter to QEMU if you want more memory:
307 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
309 This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
310 supports 3 GiB maximum system memory and reserves the last 1 GiB address space
311 for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
314 QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
315 show QEMU's VGA console window. Note this will disable QEMU's serial output.
316 If you want to check both consoles, use '-serial stdio'.
318 Multicore is also supported by QEMU via '-smp n' where n is the number of cores
319 to instantiate. Note, the maximum supported CPU number in QEMU is 255.
321 The fw_cfg interface in QEMU also provides information about kernel data, initrd,
322 command-line arguments and more. U-Boot supports directly accessing these informtion
323 from fw_cfg interface, this saves the time of loading them from hard disk or
324 network again, through emulated devices. To use it , simply providing them in
327 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
328 -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
330 Note: -initrd and -smp are both optional
332 Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel:
335 qfw - QEMU firmware interface
339 - list : print firmware(s) currently loaded
340 - cpus : print online cpu number
341 - load <kernel addr> <initrd addr> : load kernel and initrd (if any) and setup for zboot
344 loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
346 Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot'
347 can be used to boot the kernel:
349 => zboot 02000000 - 04000000 1b1ab50
353 Modern CPUs usually require a special bit stream called microcode [8] to be
354 loaded on the processor after power up in order to function properly. U-Boot
355 has already integrated these as hex dumps in the source tree.
359 On a multicore system, U-Boot is executed on the bootstrap processor (BSP).
360 Additional application processors (AP) can be brought up by U-Boot. In order to
361 have an SMP kernel to discover all of the available processors, U-Boot needs to
362 prepare configuration tables which contain the multi-CPUs information before
363 loading the OS kernel. Currently U-Boot supports generating two types of tables
364 for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP)
365 [10] tables. The writing of these two tables are controlled by two Kconfig
366 options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
370 x86 has been converted to use driver model for serial and GPIO.
374 x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
375 be turned on. Not every device on the board is configured via device tree, but
376 more and more devices will be added as time goes by. Check out the directory
377 arch/x86/dts/ for these device tree source files.
381 In keeping with the U-Boot philosophy of providing functions to check and
382 adjust internal settings, there are several x86-specific commands that may be
385 fsp - Display information about Intel Firmware Support Package (FSP).
386 This is only available on platforms which use FSP, mostly Atom.
387 iod - Display I/O memory
388 iow - Write I/O memory
389 mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
390 tell the CPU whether memory is cacheable and if so the cache write
391 mode to use. U-Boot sets up some reasonable values but you can
392 adjust then with this command.
396 As an example of how to set up your boot flow with U-Boot, here are
397 instructions for starting Ubuntu from U-Boot. These instructions have been
398 tested on Minnowboard MAX with a SATA driver but are equally applicable on
399 other platforms and other media. There are really only four steps and its a
400 very simple script, but a more detailed explanation is provided here for
403 Note: It is possible to set up U-Boot to boot automatically using syslinux.
404 It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
405 GUID. If you figure these out, please post patches to this README.
407 Firstly, you will need Ubunutu installed on an available disk. It should be
408 possible to make U-Boot start a USB start-up disk but for now let's assume
409 that you used another boot loader to install Ubuntu.
411 Use the U-Boot command line to find the UUID of the partition you want to
412 boot. For example our disk is SCSI device 0:
416 Partition Map for SCSI device 0 -- Partition Type: EFI
418 Part Start LBA End LBA Name
422 1 0x00000800 0x001007ff ""
423 attrs: 0x0000000000000000
424 type: c12a7328-f81f-11d2-ba4b-00a0c93ec93b
425 guid: 9d02e8e4-4d59-408f-a9b0-fd497bc9291c
426 2 0x00100800 0x037d8fff ""
427 attrs: 0x0000000000000000
428 type: 0fc63daf-8483-4772-8e79-3d69d8477de4
429 guid: 965c59ee-1822-4326-90d2-b02446050059
430 3 0x037d9000 0x03ba27ff ""
431 attrs: 0x0000000000000000
432 type: 0657fd6d-a4ab-43c4-84e5-0933c84b4f4f
433 guid: 2c4282bd-1e82-4bcf-a5ff-51dedbf39f17
436 This shows that your SCSI disk has three partitions. The really long hex
437 strings are called Globally Unique Identifiers (GUIDs). You can look up the
438 'type' ones here [11]. On this disk the first partition is for EFI and is in
439 VFAT format (DOS/Windows):
447 Partition 2 is 'Linux filesystem data' so that will be our root disk. It is
453 <DIR> 16384 lost+found
476 <SYM> 33 initrd.img.old
479 and if you look in the /boot directory you will see the kernel:
481 => ext2ls scsi 0:2 /boot
486 3381262 System.map-3.13.0-32-generic
487 1162712 abi-3.13.0-32-generic
488 165611 config-3.13.0-32-generic
489 176500 memtest86+.bin
490 178176 memtest86+.elf
491 178680 memtest86+_multiboot.bin
492 5798112 vmlinuz-3.13.0-32-generic
493 165762 config-3.13.0-58-generic
494 1165129 abi-3.13.0-58-generic
495 5823136 vmlinuz-3.13.0-58-generic
496 19215259 initrd.img-3.13.0-58-generic
497 3391763 System.map-3.13.0-58-generic
498 5825048 vmlinuz-3.13.0-58-generic.efi.signed
499 28304443 initrd.img-3.13.0-32-generic
502 The 'vmlinuz' files contain a packaged Linux kernel. The format is a kind of
503 self-extracting compressed file mixed with some 'setup' configuration data.
504 Despite its size (uncompressed it is >10MB) this only includes a basic set of
505 device drivers, enough to boot on most hardware types.
507 The 'initrd' files contain a RAM disk. This is something that can be loaded
508 into RAM and will appear to Linux like a disk. Ubuntu uses this to hold lots
509 of drivers for whatever hardware you might have. It is loaded before the
510 real root disk is accessed.
512 The numbers after the end of each file are the version. Here it is Linux
513 version 3.13. You can find the source code for this in the Linux tree with
514 the tag v3.13. The '.0' allows for additional Linux releases to fix problems,
515 but normally this is not needed. The '-58' is used by Ubuntu. Each time they
516 release a new kernel they increment this number. New Ubuntu versions might
517 include kernel patches to fix reported bugs. Stable kernels can exist for
518 some years so this number can get quite high.
520 The '.efi.signed' kernel is signed for EFI's secure boot. U-Boot has its own
521 secure boot mechanism - see [12] [13] and cannot read .efi files at present.
523 To boot Ubuntu from U-Boot the steps are as follows:
525 1. Set up the boot arguments. Use the GUID for the partition you want to
528 => setenv bootargs root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
530 Here root= tells Linux the location of its root disk. The disk is specified
531 by its GUID, using '/dev/disk/by-partuuid/', a Linux path to a 'directory'
532 containing all the GUIDs Linux has found. When it starts up, there will be a
533 file in that directory with this name in it. It is also possible to use a
534 device name here, see later.
536 2. Load the kernel. Since it is an ext2/4 filesystem we can do:
538 => ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic
540 The address 30000000 is arbitrary, but there seem to be problems with using
541 small addresses (sometimes Linux cannot find the ramdisk). This is 48MB into
542 the start of RAM (which is at 0 on x86).
544 3. Load the ramdisk (to 64MB):
546 => ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic
548 4. Start up the kernel. We need to know the size of the ramdisk, but can use
549 a variable for that. U-Boot sets 'filesize' to the size of the last file it
552 => zboot 03000000 0 04000000 ${filesize}
554 Type 'help zboot' if you want to see what the arguments are. U-Boot on x86 is
555 quite verbose when it boots a kernel. You should see these messages from
559 Setup Size = 0x00004400
560 Magic signature found
561 Using boot protocol version 2.0c
562 Linux kernel version 3.13.0-58-generic (buildd@allspice) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015
563 Building boot_params at 0x00090000
564 Loading bzImage at address 100000 (5805728 bytes)
565 Magic signature found
566 Initial RAM disk at linear address 0x04000000, size 19215259 bytes
567 Kernel command line: "console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
571 U-Boot prints out some bootstage timing. This is more useful if you put the
572 above commands into a script since then it will be faster.
574 Timer summary in microseconds:
577 241,535 241,535 board_init_r
578 2,421,611 2,180,076 id=64
580 2,428,215 6,425 main_loop
581 48,860,584 46,432,369 start_kernel
585 1,422,704 vesa display
587 Now the kernel actually starts:
589 [ 0.000000] Initializing cgroup subsys cpuset
590 [ 0.000000] Initializing cgroup subsys cpu
591 [ 0.000000] Initializing cgroup subsys cpuacct
592 [ 0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
593 [ 0.000000] Command line: console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
595 It continues for a long time. Along the way you will see it pick up your
598 [ 0.000000] RAMDISK: [mem 0x04000000-0x05253fff]
600 [ 0.788540] Trying to unpack rootfs image as initramfs...
601 [ 1.540111] Freeing initrd memory: 18768K (ffff880004000000 - ffff880005254000)
604 Later it actually starts using it:
606 Begin: Running /scripts/local-premount ... done.
608 You should also see your boot disk turn up:
610 [ 4.357243] scsi 1:0:0:0: Direct-Access ATA ADATA SP310 5.2 PQ: 0 ANSI: 5
611 [ 4.366860] sd 1:0:0:0: [sda] 62533296 512-byte logical blocks: (32.0 GB/29.8 GiB)
612 [ 4.375677] sd 1:0:0:0: Attached scsi generic sg0 type 0
613 [ 4.381859] sd 1:0:0:0: [sda] Write Protect is off
614 [ 4.387452] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
615 [ 4.399535] sda: sda1 sda2 sda3
617 Linux has found the three partitions (sda1-3). Mercifully it doesn't print out
618 the GUIDs. In step 1 above we could have used:
620 setenv bootargs root=/dev/sda2 ro
622 instead of the GUID. However if you add another drive to your board the
623 numbering may change whereas the GUIDs will not. So if your boot partition
624 becomes sdb2, it will still boot. For embedded systems where you just want to
625 boot the first disk, you have that option.
627 The last thing you will see on the console is mention of plymouth (which
628 displays the Ubuntu start-up screen) and a lot of 'Starting' messages:
630 * Starting Mount filesystems on boot [ OK ]
632 After a pause you should see a login screen on your display and you are done.
634 If you want to put this in a script you can use something like this:
636 setenv bootargs root=UUID=b2aaf743-0418-4d90-94cc-3e6108d7d968 ro
637 setenv boot zboot 03000000 0 04000000 \${filesize}
638 setenv bootcmd "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; run boot"
641 The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
644 You will also need to add this to your board configuration file, e.g.
645 include/configs/minnowmax.h:
647 #define CONFIG_BOOTDELAY 2
649 Now when you reset your board it wait a few seconds (in case you want to
650 interrupt) and then should boot straight into Ubuntu.
652 You can also bake this behaviour into your build by hard-coding the
653 environment variables if you add this to minnowmax.h:
655 #undef CONFIG_BOOTARGS
656 #undef CONFIG_BOOTCOMMAND
658 #define CONFIG_BOOTARGS \
660 #define CONFIG_BOOTCOMMAND \
661 "ext2load scsi 0:2 03000000 /boot/vmlinuz-3.13.0-58-generic; " \
662 "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \
665 #undef CONFIG_EXTRA_ENV_SETTINGS
666 #define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}"
671 These notes are for those who want to port U-Boot to a new x86 platform.
673 Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
674 The Dediprog em100 can be used on Linux. The em100 tool is available here:
676 http://review.coreboot.org/p/em100.git
678 On Minnowboard Max the following command line can be used:
680 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
682 A suitable clip for connecting over the SPI flash chip is here:
684 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
686 This allows you to override the SPI flash contents for development purposes.
687 Typically you can write to the em100 in around 1200ms, considerably faster
688 than programming the real flash device each time. The only important
689 limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
690 This means that images must be set to boot with that speed. This is an
691 Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
692 speed in the SPI descriptor region.
694 If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
695 easy to fit it in. You can follow the Minnowboard Max implementation, for
696 example. Hopefully you will just need to create new files similar to those
697 in arch/x86/cpu/baytrail which provide Bay Trail support.
699 If you are not using an FSP you have more freedom and more responsibility.
700 The ivybridge support works this way, although it still uses a ROM for
701 graphics and still has binary blobs containing Intel code. You should aim to
702 support all important peripherals on your platform including video and storage.
703 Use the device tree for configuration where possible.
705 For the microcode you can create a suitable device tree file using the
708 ./tools/microcode-tool -d microcode.dat -m <model> create
710 or if you only have header files and not the full Intel microcode.dat database:
712 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
713 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
716 These are written to arch/x86/dts/microcode/ by default.
718 Note that it is possible to just add the micrcode for your CPU if you know its
719 model. U-Boot prints this information when it starts
721 CPU: x86_64, vendor Intel, device 30673h
723 so here we can use the M0130673322 file.
725 If you platform can display POST codes on two little 7-segment displays on
726 the board, then you can use post_code() calls from C or assembler to monitor
727 boot progress. This can be good for debugging.
729 If not, you can try to get serial working as early as possible. The early
730 debug serial port may be useful here. See setup_internal_uart() for an example.
732 During the U-Boot porting, one of the important steps is to write correct PIRQ
733 routing information in the board device tree. Without it, device drivers in the
734 Linux kernel won't function correctly due to interrupt is not working. Please
735 refer to U-Boot doc [14] for the device tree bindings of Intel interrupt router.
736 Here we have more details on the intel,pirq-routing property below.
738 intel,pirq-routing = <
739 PCI_BDF(0, 2, 0) INTA PIRQA
743 As you see each entry has 3 cells. For the first one, we need describe all pci
744 devices mounted on the board. For SoC devices, normally there is a chapter on
745 the chipset datasheet which lists all the available PCI devices. For example on
746 Bay Trail, this is chapter 4.3 (PCI configuration space). For the second one, we
747 can get the interrupt pin either from datasheet or hardware via U-Boot shell.
748 The reliable source is the hardware as sometimes chipset datasheet is not 100%
749 up-to-date. Type 'pci header' plus the device's pci bus/device/function number
750 from U-Boot shell below.
756 interrupt line = 0x09
760 It shows this PCI device is using INTD pin as it reports 4 in the interrupt pin
761 register. Repeat this until you get interrupt pins for all the devices. The last
762 cell is the PIRQ line which a particular interrupt pin is mapped to. On Intel
763 chipset, the power-up default mapping is INTA/B/C/D maps to PIRQA/B/C/D. This
764 can be changed by registers in LPC bridge. So far Intel FSP does not touch those
765 registers so we can write down the PIRQ according to the default mapping rule.
767 Once we get the PIRQ routing information in the device tree, the interrupt
768 allocation and assignment will be done by U-Boot automatically. Now you can
769 enable CONFIG_GENERATE_PIRQ_TABLE for testing Linux kernel using i8259 PIC and
770 CONFIG_GENERATE_MP_TABLE for testing Linux kernel using local APIC and I/O APIC.
772 This script might be useful. If you feed it the output of 'pci long' from
773 U-Boot then it will generate a device tree fragment with the interrupt
774 configuration for each device (note it needs gawk 4.0.0):
776 $ cat console_output |awk '/PCI/ {device=$4} /interrupt line/ {line=$4} \
777 /interrupt pin/ {pin = $4; if (pin != "0x00" && pin != "0xff") \
778 {patsplit(device, bdf, "[0-9a-f]+"); \
779 printf "PCI_BDF(%d, %d, %d) INT%c PIRQ%c\n", strtonum("0x" bdf[1]), \
780 strtonum("0x" bdf[2]), bdf[3], strtonum(pin) + 64, 64 + strtonum(pin)}}'
783 PCI_BDF(0, 2, 0) INTA PIRQA
784 PCI_BDF(0, 3, 0) INTA PIRQA
790 Quark-specific considerations:
792 To port U-Boot to other boards based on the Intel Quark SoC, a few things need
793 to be taken care of. The first important part is the Memory Reference Code (MRC)
794 parameters. Quark MRC supports memory-down configuration only. All these MRC
795 parameters are supplied via the board device tree. To get started, first copy
796 the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then
797 change these values by consulting board manuals or your hardware vendor.
798 Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h.
799 The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports,
800 but by default they are held in reset after power on. In U-Boot, PCIe
801 initialization is properly handled as per Quark's firmware writer guide.
802 In your board support codes, you need provide two routines to aid PCIe
803 initialization, which are board_assert_perst() and board_deassert_perst().
804 The two routines need implement a board-specific mechanism to assert/deassert
805 PCIe PERST# pin. Care must be taken that in those routines that any APIs that
806 may trigger PCI enumeration process are strictly forbidden, as any access to
807 PCIe root port's configuration registers will cause system hang while it is
808 held in reset. For more details, check how they are implemented by the Intel
809 Galileo board support codes in board/intel/galileo/galileo.c.
814 - Chrome OS verified boot
815 - SMI and ACPI support, to provide platform info and facilities to Linux
819 [1] http://www.coreboot.org
820 [2] http://www.qemu.org
821 [3] http://www.coreboot.org/~stepan/pci8086,0166.rom
822 [4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
823 [5] http://www.intel.com/fsp
824 [6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
825 [7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
826 [8] http://en.wikipedia.org/wiki/Microcode
827 [9] http://simplefirmware.org
828 [10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm
829 [11] https://en.wikipedia.org/wiki/GUID_Partition_Table
830 [12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
831 [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
832 [14] doc/device-tree-bindings/misc/intel,irq-router.txt