board/wandboard/wandboard.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2014 O.S. Systems Software LTDA.
   5  *
   6  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <asm/mach-imx/sata.h>
  22 #include <asm/io.h>
  23 #include <env.h>
  24 #include <linux/sizes.h>
  25 #include <common.h>
  26 #include <miiphy.h>
  27 #include <netdev.h>
  28 #include <phy.h>
  29 #include <i2c.h>
  30 #include <power/pmic.h>
  31 #include <power/pfuze100_pmic.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  36         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  37         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  40         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  41
  42 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  43         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  44         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  45
  46 #define ETH_PHY_RESET           IMX_GPIO_NR(3, 29)
  47 #define ETH_PHY_AR8035_POWER    IMX_GPIO_NR(7, 13)
  48 #define REV_DETECTION           IMX_GPIO_NR(2, 28)
  49
  50 /* Speed defined in Kconfig is only applicable when not using DM_I2C.  */
  51 #ifdef CONFIG_DM_I2C
  52 #define I2C1_SPEED_NON_DM       0
  53 #define I2C2_SPEED_NON_DM       0
  54 #else
  55 #define I2C1_SPEED_NON_DM       CONFIG_SYS_MXC_I2C1_SPEED
  56 #define I2C2_SPEED_NON_DM       CONFIG_SYS_MXC_I2C2_SPEED
  57 #endif
  58
  59 static bool with_pmic;
  60
  61 int dram_init(void)
  62 {
  63         gd->ram_size = imx_ddr_size();
  64
  65         return 0;
  66 }
  67
  68 static iomux_v3_cfg_t const uart1_pads[] = {
  69         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  70         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  71 };
  72
  73 static iomux_v3_cfg_t const enet_pads[] = {
  74         /* AR8031 PHY Reset */
  75         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  76 };
  77
  78 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
  79         /* AR8035 POWER */
  80         IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  81 };
  82
  83 static iomux_v3_cfg_t const rev_detection_pad[] = {
  84         IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28  | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85 };
  86
  87 static void setup_iomux_uart(void)
  88 {
  89         SETUP_IOMUX_PADS(uart1_pads);
  90 }
  91
  92 static void setup_iomux_enet(void)
  93 {
  94         SETUP_IOMUX_PADS(enet_pads);
  95
  96         if (with_pmic) {
  97                 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
  98                 /* enable AR8035 POWER */
  99                 gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
 100                 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
 101         }
 102         /* wait until 3.3V of PHY and clock become stable */
 103         mdelay(10);
 104
 105         /* Reset AR8031 PHY */
 106         gpio_request(ETH_PHY_RESET, "PHY_RESET");
 107         gpio_direction_output(ETH_PHY_RESET, 0);
 108         mdelay(10);
 109         gpio_set_value(ETH_PHY_RESET, 1);
 110         udelay(100);
 111 }
 112
 113 static int ar8031_phy_fixup(struct phy_device *phydev)
 114 {
 115         unsigned short val;
 116         int mask;
 117
 118         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 119         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 120         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 121         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 122
 123         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 124         if (with_pmic)
 125                 mask = 0xffe7;  /* AR8035 */
 126         else
 127                 mask = 0xffe3;  /* AR8031 */
 128
 129         val &= mask;
 130         val |= 0x18;
 131         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 132
 133         /* introduce tx clock delay */
 134         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 135         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 136         val |= 0x0100;
 137         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 138
 139         return 0;
 140 }
 141
 142 int board_phy_config(struct phy_device *phydev)
 143 {
 144         ar8031_phy_fixup(phydev);
 145
 146         if (phydev->drv->config)
 147                 phydev->drv->config(phydev);
 148
 149         return 0;
 150 }
 151
 152 #if defined(CONFIG_VIDEO_IPUV3)
 153 struct i2c_pads_info mx6q_i2c2_pad_info = {
 154         .scl = {
 155                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
 156                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 157                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
 158                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 159                 .gp = IMX_GPIO_NR(4, 12)
 160         },
 161         .sda = {
 162                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
 163                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 164                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
 165                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 166                 .gp = IMX_GPIO_NR(4, 13)
 167         }
 168 };
 169
 170 struct i2c_pads_info mx6dl_i2c2_pad_info = {
 171         .scl = {
 172                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
 173                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 174                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
 175                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 176                 .gp = IMX_GPIO_NR(4, 12)
 177         },
 178         .sda = {
 179                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
 180                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 181                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
 182                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 183                 .gp = IMX_GPIO_NR(4, 13)
 184         }
 185 };
 186
 187 struct i2c_pads_info mx6q_i2c3_pad_info = {
 188         .scl = {
 189                 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
 190                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 191                 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
 192                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 193                 .gp = IMX_GPIO_NR(1, 5)
 194         },
 195         .sda = {
 196                 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
 197                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 198                 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
 199                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 200                 .gp = IMX_GPIO_NR(7, 11)
 201         }
 202 };
 203
 204 struct i2c_pads_info mx6dl_i2c3_pad_info = {
 205         .scl = {
 206                 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
 207                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 208                 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
 209                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 210                 .gp = IMX_GPIO_NR(1, 5)
 211         },
 212         .sda = {
 213                 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
 214                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 215                 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
 216                         | MUX_PAD_CTRL(I2C_PAD_CTRL),
 217                 .gp = IMX_GPIO_NR(7, 11)
 218         }
 219 };
 220
 221 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
 222         IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 223         IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
 224         IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
 225         IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
 226         IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
 227         IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
 228         IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
 229         IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
 230         IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
 231         IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
 232         IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
 233         IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
 234         IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
 235         IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
 236         IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
 237         IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
 238         IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
 239         IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
 240         IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
 241         IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
 242         IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
 243         IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
 244         IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
 245         IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
 246         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
 247 };
 248
 249 static void do_enable_hdmi(struct display_info_t const *dev)
 250 {
 251         imx_enable_hdmi_phy();
 252 }
 253
 254 static int detect_i2c(struct display_info_t const *dev)
 255 {
 256 #ifdef CONFIG_DM_I2C
 257         struct udevice *bus, *udev;
 258         int rc;
 259
 260         rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
 261         if (rc)
 262                 return rc;
 263         rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
 264         if (rc)
 265                 return 0;
 266         return 1;
 267 #else
 268         return (0 == i2c_set_bus_num(dev->bus)) &&
 269                         (0 == i2c_probe(dev->addr));
 270 #endif
 271 }
 272
 273 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
 274 {
 275         SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
 276
 277         gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
 278         gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
 279         gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
 280         gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
 281 }
 282
 283 struct display_info_t const displays[] = {{
 284         .bus    = -1,
 285         .addr   = 0,
 286         .pixfmt = IPU_PIX_FMT_RGB24,
 287         .detect = detect_hdmi,
 288         .enable = do_enable_hdmi,
 289         .mode   = {
 290                 .name           = "HDMI",
 291                 .refresh        = 60,
 292                 .xres           = 1024,
 293                 .yres           = 768,
 294                 .pixclock       = 15385,
 295                 .left_margin    = 220,
 296                 .right_margin   = 40,
 297                 .upper_margin   = 21,
 298                 .lower_margin   = 7,
 299                 .hsync_len      = 60,
 300                 .vsync_len      = 10,
 301                 .sync           = FB_SYNC_EXT,
 302                 .vmode          = FB_VMODE_NONINTERLACED
 303 } }, {
 304         .bus    = 1,
 305         .addr   = 0x10,
 306         .pixfmt = IPU_PIX_FMT_RGB666,
 307         .detect = detect_i2c,
 308         .enable = enable_fwadapt_7wvga,
 309         .mode   = {
 310                 .name           = "FWBADAPT-LCD-F07A-0102",
 311                 .refresh        = 60,
 312                 .xres           = 800,
 313                 .yres           = 480,
 314                 .pixclock       = 33260,
 315                 .left_margin    = 128,
 316                 .right_margin   = 128,
 317                 .upper_margin   = 22,
 318                 .lower_margin   = 22,
 319                 .hsync_len      = 1,
 320                 .vsync_len      = 1,
 321                 .sync           = 0,
 322                 .vmode          = FB_VMODE_NONINTERLACED
 323 } } };
 324 size_t display_count = ARRAY_SIZE(displays);
 325
 326 static void setup_display(void)
 327 {
 328         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 329         int reg;
 330
 331         enable_ipu_clock();
 332         imx_setup_hdmi();
 333
 334         reg = readl(&mxc_ccm->chsccdr);
 335         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 336                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 337         writel(reg, &mxc_ccm->chsccdr);
 338
 339         /* Disable LCD backlight */
 340         SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
 341         gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
 342         gpio_direction_input(IMX_GPIO_NR(4, 20));
 343 }
 344 #endif /* CONFIG_VIDEO_IPUV3 */
 345
 346 int board_early_init_f(void)
 347 {
 348         setup_iomux_uart();
 349 #ifdef CONFIG_SATA
 350         setup_sata();
 351 #endif
 352
 353         return 0;
 354 }
 355
 356 #define PMIC_I2C_BUS            2
 357
 358 int power_init_board(void)
 359 {
 360         struct udevice *dev;
 361         int reg, ret;
 362
 363         puts("PMIC:  ");
 364
 365         ret = pmic_get("pfuze100", &dev);
 366         if (ret < 0) {
 367                 printf("pmic_get() ret %d\n", ret);
 368                 return 0;
 369         }
 370
 371         reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
 372         if (reg < 0) {
 373                 printf("pmic_reg_read() ret %d\n", reg);
 374                 return 0;
 375         }
 376         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 377         with_pmic = true;
 378
 379         /* Set VGEN2 to 1.5V and enable */
 380         reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
 381         reg &= ~(LDO_VOL_MASK);
 382         reg |= (LDOA_1_50V | (1 << (LDO_EN)));
 383         pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
 384         return 0;
 385 }
 386
 387 /*
 388  * Do not overwrite the console
 389  * Use always serial for U-Boot console
 390  */
 391 int overwrite_console(void)
 392 {
 393         return 1;
 394 }
 395
 396 #ifdef CONFIG_CMD_BMODE
 397 static const struct boot_mode board_boot_modes[] = {
 398         /* 4 bit bus width */
 399         {"mmc0",          MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 400         {"mmc1",          MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 401         {NULL,   0},
 402 };
 403 #endif
 404
 405 static bool is_revc1(void)
 406 {
 407         SETUP_IOMUX_PADS(rev_detection_pad);
 408         gpio_direction_input(REV_DETECTION);
 409
 410         if (gpio_get_value(REV_DETECTION))
 411                 return true;
 412         else
 413                 return false;
 414 }
 415
 416 static bool is_revd1(void)
 417 {
 418         if (with_pmic)
 419                 return true;
 420         else
 421                 return false;
 422 }
 423
 424 int board_late_init(void)
 425 {
 426 #ifdef CONFIG_CMD_BMODE
 427         add_board_boot_modes(board_boot_modes);
 428 #endif
 429
 430 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 431         if (is_mx6dqp())
 432                 env_set("board_rev", "MX6QP");
 433         else if (is_mx6dq())
 434                 env_set("board_rev", "MX6Q");
 435         else
 436                 env_set("board_rev", "MX6DL");
 437
 438         if (is_revd1())
 439                 env_set("board_name", "D1");
 440         else if (is_revc1())
 441                 env_set("board_name", "C1");
 442         else
 443                 env_set("board_name", "B1");
 444 #endif
 445         setup_iomux_enet();
 446         return 0;
 447 }
 448
 449 int board_init(void)
 450 {
 451         /* address of boot parameters */
 452         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 453
 454 #if defined(CONFIG_VIDEO_IPUV3)
 455         setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
 456         if (is_mx6dq() || is_mx6dqp()) {
 457                 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
 458                 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
 459         } else {
 460                 setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
 461                 setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
 462         }
 463
 464         setup_display();
 465 #endif
 466
 467         return 0;
 468 }
 469
 470 int checkboard(void)
 471 {
 472         gpio_request(REV_DETECTION, "REV_DETECT");
 473
 474         if (is_revd1())
 475                 puts("Board: Wandboard rev D1\n");
 476         else if (is_revc1())
 477                 puts("Board: Wandboard rev C1\n");
 478         else
 479                 puts("Board: Wandboard rev B1\n");
 480
 481         return 0;
 482 }
 483
 484 #ifdef CONFIG_SPL_LOAD_FIT
 485 int board_fit_config_name_match(const char *name)
 486 {
 487         if (is_mx6dq()) {
 488                 if (!strcmp(name, "imx6q-wandboard-revb1"))
 489                         return 0;
 490         } else if (is_mx6dqp()) {
 491                 if (!strcmp(name, "imx6qp-wandboard-revd1"))
 492                         return 0;
 493         } else if (is_mx6dl() || is_mx6solo()) {
 494                 if (!strcmp(name, "imx6dl-wandboard-revb1"))
 495                         return 0;
 496         }
 497
 498         return -EINVAL;
 499 }
 500 #endif