board/toradex/colibri_imx6/pf0100_otp.inc

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014-2016, Toradex AG
   4  */
   5
   6 // Register Output for PF0100 programmer
   7 // Customer: Toradex AG
   8 // Program: Colibri iMX6
   9 // Sample marking:
  10 // Date: 24.07.2015
  11 // Time: 10:52:58
  12 // Generated from Spreadsheet Revision: P1.8
  13
  14 /* sed commands to get from programmer script to struct */
  15 /* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc
  16    sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
  17    sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
  18
  19 enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
  20 struct pmic_otp_prog_t{
  21         unsigned char cmd;
  22         unsigned char reg;
  23         unsigned short value;
  24 };
  25
  26 struct pmic_otp_prog_t pmic_otp_prog[] = {
  27 {pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
  28 {pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
  29 {pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
  30 {pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
  31 {pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
  32 {pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
  33 {pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
  34 {pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
  35 {pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
  36 {pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
  37 {pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
  38 {pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
  39 {pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
  40 {pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
  41 {pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
  42 {pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
  43 {pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
  44 {pmic_i2c, 0xBD, 0x0E}, // Auto gen from Row123
  45 {pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
  46 {pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
  47 {pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
  48 {pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
  49 {pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
  50 {pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
  51 {pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
  52 {pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
  53 {pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
  54 {pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
  55 {pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
  56 {pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158
  57
  58 #if 0 /* TBB mode */
  59 {pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
  60 {pmic_delay, 0, 10},
  61 #else
  62 // Write OTP
  63 {pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
  64 {pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
  65 {pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
  66 {pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
  67 {pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
  68 {pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
  69 {pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
  70 {pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
  71 //-----------------------------------------------------------------------------------
  72 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  73 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  74 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  75 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  76 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  77 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  78 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  79 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  80 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  81 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  82 //-----------------------------------------------------------------------------------
  83 {pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
  84 //VPGM:DOWN:n
  85 //VPGM:UP:n
  86 {pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
  87 //-----------------------------------------------------------------------------------
  88 // PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
  89 //-----------------------------------------------------------------------------------
  90 // BANK 1
  91 //-----------------------------------------------------------------------------------
  92 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  93 {pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  94 {pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
  95 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
  96 {pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
  97 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
  98 //-----------------------------------------------------------------------------------
  99 // BANK 2
 100 //-----------------------------------------------------------------------------------
 101 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 102 {pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 103 {pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
 104 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
 105 {pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
 106 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 107 //-----------------------------------------------------------------------------------
 108 // BANK 3
 109 //-----------------------------------------------------------------------------------
 110 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 111 {pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 112 {pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
 113 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
 114 {pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
 115 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 116 //-----------------------------------------------------------------------------------
 117 // BANK 4
 118 //-----------------------------------------------------------------------------------
 119 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 120 {pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 121 {pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
 122 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
 123 {pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
 124 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 125 //-----------------------------------------------------------------------------------
 126 // BANK 5
 127 //-----------------------------------------------------------------------------------
 128 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 129 {pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 130 {pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
 131 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
 132 {pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
 133 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 134 //-----------------------------------------------------------------------------------
 135 // BANK 6
 136 //-----------------------------------------------------------------------------------
 137 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 138 {pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 139 {pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
 140 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
 141 {pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
 142 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 143 //-----------------------------------------------------------------------------------
 144 // BANK 7
 145 //-----------------------------------------------------------------------------------
 146 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 147 {pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 148 {pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
 149 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
 150 {pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
 151 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 152 //-----------------------------------------------------------------------------------
 153 // BANK 8
 154 //-----------------------------------------------------------------------------------
 155 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 156 {pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 157 {pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
 158 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
 159 {pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
 160 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 161 //-----------------------------------------------------------------------------------
 162 // BANK 9
 163 //-----------------------------------------------------------------------------------
 164 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 165 {pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 166 {pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
 167 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
 168 {pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
 169 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 170 //-----------------------------------------------------------------------------------
 171 // BANK 10
 172 //-----------------------------------------------------------------------------------
 173 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 174 {pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 175 {pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
 176 {pmic_delay, 0, 10}, // Allow time for bank programming to complete
 177 {pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
 178 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
 179 //-----------------------------------------------------------------------------------
 180 {pmic_vpgm, 0, 0}, // Turn off 8V SWBST
 181 {pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
 182 {pmic_i2c, 0xD0, 0x00}, // Clear
 183 {pmic_i2c, 0xD1, 0x00}, // Clear
 184 {pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
 185 {pmic_delay, 0, 500},
 186 {pmic_pwr, 0, 1},
 187 #endif
 188 };