board/toradex/colibri_imx6/colibri_imx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  * Copyright (C) 2014-2019, Toradex AG
   6  * copied from nitrogen6x
   7  */
   8
   9 #include <common.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <env.h>
  13 #include <init.h>
  14 #include <net.h>
  15 #include <asm/global_data.h>
  16 #include <linux/bitops.h>
  17 #include <linux/delay.h>
  18
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/crm_regs.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include <asm/arch/mx6-ddr.h>
  23 #include <asm/arch/mx6-pins.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/bootm.h>
  27 #include <asm/gpio.h>
  28 #include <asm/mach-imx/boot_mode.h>
  29 #include <asm/mach-imx/iomux-v3.h>
  30 #include <asm/mach-imx/sata.h>
  31 #include <asm/mach-imx/video.h>
  32 #include <cpu.h>
  33 #include <dm/platform_data/serial_mxc.h>
  34 #include <fsl_esdhc_imx.h>
  35 #include <imx_thermal.h>
  36 #include <miiphy.h>
  37 #include <netdev.h>
  38 #include <cpu.h>
  39
  40 #include "../common/tdx-cfg-block.h"
  41 #ifdef CONFIG_TDX_CMD_IMX_MFGR
  42 #include "pf0100.h"
  43 #endif
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  48         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  49         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  50
  51 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  52         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |                 \
  53         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  54
  55 #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
  56         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  57         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  58
  59 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_SRE_SLOW)
  62
  63 #define NO_PULLUP       (                                       \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  65         PAD_CTL_SRE_SLOW)
  66
  67 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  68         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  69         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  70
  71 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  72
  73 int dram_init(void)
  74 {
  75         /* use the DDR controllers configured size */
  76         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  77                                     (ulong)imx_ddr_size());
  78
  79         return 0;
  80 }
  81
  82 /* Colibri UARTA */
  83 iomux_v3_cfg_t const uart1_pads[] = {
  84         MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  85         MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  86 };
  87
  88 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
  89 /* Colibri MMC */
  90 iomux_v3_cfg_t const usdhc1_pads[] = {
  91         MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  98 #       define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  99 };
 100
 101 /* eMMC */
 102 iomux_v3_cfg_t const usdhc3_pads[] = {
 103         MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 104         MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 105         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 106         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 107         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 108         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 109         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 110         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 111         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 112         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 113         MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114 };
 115 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 116
 117 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
 118 iomux_v3_cfg_t const gpio_pads[] = {
 119         /* ADDRESS[17:18] [25] used as GPIO */
 120         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 121                                           MUX_MODE_SION,
 122         MX6_PAD_KEY_COL2__GPIO4_IO10    | MUX_PAD_CTRL(WEAK_PULLUP) |
 123                                           MUX_MODE_SION,
 124         MX6_PAD_NANDF_D1__GPIO2_IO01    | MUX_PAD_CTRL(WEAK_PULLUP) |
 125                                           MUX_MODE_SION,
 126         /* ADDRESS[19:24] used as GPIO */
 127         MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
 128                                           MUX_MODE_SION,
 129         MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
 130                                           MUX_MODE_SION,
 131         MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
 132                                           MUX_MODE_SION,
 133         MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
 134                                           MUX_MODE_SION,
 135         MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
 136                                           MUX_MODE_SION,
 137         MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
 138                                           MUX_MODE_SION,
 139         /* DATA[16:29] [31]      used as GPIO */
 140         MX6_PAD_EIM_LBA__GPIO2_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 141                                           MUX_MODE_SION,
 142         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(WEAK_PULLUP) |
 143                                           MUX_MODE_SION,
 144         MX6_PAD_NANDF_CS3__GPIO6_IO16   | MUX_PAD_CTRL(WEAK_PULLUP) |
 145                                           MUX_MODE_SION,
 146         MX6_PAD_NANDF_CS1__GPIO6_IO14   | MUX_PAD_CTRL(WEAK_PULLUP) |
 147                                           MUX_MODE_SION,
 148         MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(WEAK_PULLUP) |
 149                                           MUX_MODE_SION,
 150         MX6_PAD_NANDF_ALE__GPIO6_IO08   | MUX_PAD_CTRL(WEAK_PULLUP) |
 151                                           MUX_MODE_SION,
 152         MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(WEAK_PULLUP) |
 153                                           MUX_MODE_SION,
 154         MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(WEAK_PULLUP) |
 155                                           MUX_MODE_SION,
 156         MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(WEAK_PULLUP) |
 157                                           MUX_MODE_SION,
 158         MX6_PAD_GPIO_19__GPIO4_IO05     | MUX_PAD_CTRL(WEAK_PULLUP) |
 159                                           MUX_MODE_SION,
 160         MX6_PAD_CSI0_MCLK__GPIO5_IO19   | MUX_PAD_CTRL(WEAK_PULLUP) |
 161                                           MUX_MODE_SION,
 162         MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
 163                                           MUX_MODE_SION,
 164         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(WEAK_PULLUP) |
 165                                           MUX_MODE_SION,
 166         MX6_PAD_GPIO_5__GPIO1_IO05      | MUX_PAD_CTRL(WEAK_PULLUP) |
 167                                           MUX_MODE_SION,
 168         MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(WEAK_PULLUP) |
 169                                           MUX_MODE_SION,
 170         /* DQM[0:3]      used as GPIO */
 171         MX6_PAD_EIM_EB0__GPIO2_IO28     | MUX_PAD_CTRL(WEAK_PULLUP) |
 172                                           MUX_MODE_SION,
 173         MX6_PAD_EIM_EB1__GPIO2_IO29     | MUX_PAD_CTRL(WEAK_PULLUP) |
 174                                           MUX_MODE_SION,
 175         MX6_PAD_SD2_DAT2__GPIO1_IO13    | MUX_PAD_CTRL(WEAK_PULLUP) |
 176                                           MUX_MODE_SION,
 177         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 178                                           MUX_MODE_SION,
 179         /* RDY  used as GPIO */
 180         MX6_PAD_EIM_WAIT__GPIO5_IO00    | MUX_PAD_CTRL(WEAK_PULLUP) |
 181                                           MUX_MODE_SION,
 182         /* ADDRESS[16] DATA[30]  used as GPIO */
 183         MX6_PAD_KEY_ROW4__GPIO4_IO15    | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 184                                           MUX_MODE_SION,
 185         MX6_PAD_KEY_COL4__GPIO4_IO14    | MUX_PAD_CTRL(WEAK_PULLUP) |
 186                                           MUX_MODE_SION,
 187         /* CSI pins used as GPIO */
 188         MX6_PAD_EIM_A24__GPIO5_IO04     | MUX_PAD_CTRL(WEAK_PULLUP) |
 189                                           MUX_MODE_SION,
 190         MX6_PAD_SD2_CMD__GPIO1_IO11     | MUX_PAD_CTRL(WEAK_PULLUP) |
 191                                           MUX_MODE_SION,
 192         MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(WEAK_PULLUP) |
 193                                           MUX_MODE_SION,
 194         MX6_PAD_EIM_D18__GPIO3_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 195                                           MUX_MODE_SION,
 196         MX6_PAD_EIM_A19__GPIO2_IO19     | MUX_PAD_CTRL(WEAK_PULLUP) |
 197                                           MUX_MODE_SION,
 198         MX6_PAD_EIM_D29__GPIO3_IO29     | MUX_PAD_CTRL(WEAK_PULLDOWN) |
 199                                           MUX_MODE_SION,
 200         MX6_PAD_EIM_A23__GPIO6_IO06     | MUX_PAD_CTRL(WEAK_PULLUP) |
 201                                           MUX_MODE_SION,
 202         MX6_PAD_EIM_A20__GPIO2_IO18     | MUX_PAD_CTRL(WEAK_PULLUP) |
 203                                           MUX_MODE_SION,
 204         MX6_PAD_EIM_A17__GPIO2_IO21     | MUX_PAD_CTRL(WEAK_PULLUP) |
 205                                           MUX_MODE_SION,
 206         MX6_PAD_EIM_A18__GPIO2_IO20     | MUX_PAD_CTRL(WEAK_PULLUP) |
 207                                           MUX_MODE_SION,
 208         MX6_PAD_EIM_EB3__GPIO2_IO31     | MUX_PAD_CTRL(WEAK_PULLUP) |
 209                                           MUX_MODE_SION,
 210         MX6_PAD_EIM_D17__GPIO3_IO17     | MUX_PAD_CTRL(WEAK_PULLUP) |
 211                                           MUX_MODE_SION,
 212         MX6_PAD_SD2_DAT0__GPIO1_IO15    | MUX_PAD_CTRL(WEAK_PULLUP) |
 213                                           MUX_MODE_SION,
 214         /* GPIO */
 215         MX6_PAD_EIM_D26__GPIO3_IO26     | MUX_PAD_CTRL(WEAK_PULLUP) |
 216                                           MUX_MODE_SION,
 217         MX6_PAD_EIM_D27__GPIO3_IO27     | MUX_PAD_CTRL(WEAK_PULLUP) |
 218                                           MUX_MODE_SION,
 219         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(WEAK_PULLUP) |
 220                                           MUX_MODE_SION,
 221         MX6_PAD_NANDF_D3__GPIO2_IO03    | MUX_PAD_CTRL(WEAK_PULLUP) |
 222                                           MUX_MODE_SION,
 223         MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
 224                                           MUX_MODE_SION,
 225         MX6_PAD_DI0_PIN4__GPIO4_IO20    | MUX_PAD_CTRL(WEAK_PULLUP) |
 226                                           MUX_MODE_SION,
 227         MX6_PAD_SD4_DAT3__GPIO2_IO11    | MUX_PAD_CTRL(WEAK_PULLUP) |
 228                                           MUX_MODE_SION,
 229         MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(WEAK_PULLUP) |
 230                                           MUX_MODE_SION,
 231         MX6_PAD_SD4_DAT0__GPIO2_IO08    | MUX_PAD_CTRL(WEAK_PULLUP) |
 232                                           MUX_MODE_SION,
 233         MX6_PAD_GPIO_7__GPIO1_IO07      | MUX_PAD_CTRL(WEAK_PULLUP) |
 234                                           MUX_MODE_SION,
 235         MX6_PAD_GPIO_8__GPIO1_IO08      | MUX_PAD_CTRL(WEAK_PULLUP) |
 236                                           MUX_MODE_SION,
 237         /* USBH_OC */
 238         MX6_PAD_EIM_D30__GPIO3_IO30     | MUX_PAD_CTRL(WEAK_PULLUP),
 239         /* USBC_ID */
 240         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(WEAK_PULLUP),
 241         /* USBC_DET */
 242         MX6_PAD_GPIO_17__GPIO7_IO12     | MUX_PAD_CTRL(WEAK_PULLUP),
 243 };
 244
 245 static void setup_iomux_gpio(void)
 246 {
 247         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 248 }
 249
 250 iomux_v3_cfg_t const usb_pads[] = {
 251         /* USBH_PEN */
 252         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 253 #       define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
 254 };
 255
 256 /*
 257  * UARTs are used in DTE mode, switch the mode on all UARTs before
 258  * any pinmuxing connects a (DCE) output to a transceiver output.
 259  */
 260 #define UCR3            0x88    /* FIFO Control Register */
 261 #define UCR3_RI         BIT(8)  /* RIDELT DTE mode */
 262 #define UCR3_DCD        BIT(9)  /* DCDDELT DTE mode */
 263 #define UFCR            0x90    /* FIFO Control Register */
 264 #define UFCR_DCEDTE     BIT(6)  /* DCE=0 */
 265
 266 static void setup_dtemode_uart(void)
 267 {
 268         setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
 269         setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
 270         setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
 271
 272         clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
 273         clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
 274         clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
 275 }
 276
 277 static void setup_iomux_uart(void)
 278 {
 279         setup_dtemode_uart();
 280         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 281 }
 282
 283 #ifdef CONFIG_USB_EHCI_MX6
 284 int board_ehci_hcd_init(int port)
 285 {
 286         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 287         return 0;
 288 }
 289 #endif
 290
 291 #if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
 292 /* use the following sequence: eMMC, MMC */
 293 struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
 294         {USDHC3_BASE_ADDR},
 295         {USDHC1_BASE_ADDR},
 296 };
 297
 298 int board_mmc_getcd(struct mmc *mmc)
 299 {
 300         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 301         int ret = true; /* default: assume inserted */
 302
 303         switch (cfg->esdhc_base) {
 304         case USDHC1_BASE_ADDR:
 305                 gpio_request(GPIO_MMC_CD, "MMC_CD");
 306                 gpio_direction_input(GPIO_MMC_CD);
 307                 ret = !gpio_get_value(GPIO_MMC_CD);
 308                 break;
 309         }
 310
 311         return ret;
 312 }
 313
 314 int board_mmc_init(struct bd_info *bis)
 315 {
 316         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 317         unsigned reg = readl(&psrc->sbmr1) >> 11;
 318         /*
 319          * Upon reading BOOT_CFG register the following map is done:
 320          * Bit 11 and 12 of BOOT_CFG register can determine the current
 321          * mmc port
 322          * 0x1                  SD1
 323          * 0x2                  SD2
 324          * 0x3                  SD4
 325          */
 326
 327         switch (reg & 0x3) {
 328         case 0x0:
 329                 imx_iomux_v3_setup_multiple_pads(
 330                         usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 331                 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
 332                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 333                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 334                 break;
 335         case 0x2:
 336                 imx_iomux_v3_setup_multiple_pads(
 337                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 338                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 339                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 340                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 341                 break;
 342         default:
 343                 puts("MMC boot device not available");
 344         }
 345
 346         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 347 }
 348 #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 349
 350 int board_phy_config(struct phy_device *phydev)
 351 {
 352         if (phydev->drv->config)
 353                 phydev->drv->config(phydev);
 354
 355         return 0;
 356 }
 357
 358 int setup_fec(void)
 359 {
 360         int ret;
 361         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 362
 363         /* provide the PHY clock from the i.MX 6 */
 364         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 365         if (ret)
 366                 return ret;
 367
 368         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 369
 370         return 0;
 371 }
 372
 373 static iomux_v3_cfg_t const pwr_intb_pads[] = {
 374         /*
 375          * the bootrom sets the iomux to vselect, potentially connecting
 376          * two outputs. Set this back to GPIO
 377          */
 378         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
 379 };
 380
 381 #if defined(CONFIG_VIDEO_IPUV3)
 382
 383 static iomux_v3_cfg_t const backlight_pads[] = {
 384         /* Backlight On */
 385         MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
 386 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
 387         /* Backlight PWM, used as GPIO in U-Boot */
 388         MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
 389         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
 390                                        MUX_MODE_SION,
 391 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
 392 };
 393
 394 static iomux_v3_cfg_t const rgb_pads[] = {
 395         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
 396         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
 397         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
 398         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
 399         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
 400         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
 401         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
 402         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
 403         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
 404         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
 405         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
 406         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
 407         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
 408         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
 409         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
 410         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
 411         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
 412         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
 413         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
 414         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
 415         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
 416         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
 417 };
 418
 419 static void do_enable_hdmi(struct display_info_t const *dev)
 420 {
 421         imx_enable_hdmi_phy();
 422 }
 423
 424 static void enable_rgb(struct display_info_t const *dev)
 425 {
 426         imx_iomux_v3_setup_multiple_pads(
 427                 rgb_pads,
 428                 ARRAY_SIZE(rgb_pads));
 429         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 430         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 431 }
 432
 433 static int detect_default(struct display_info_t const *dev)
 434 {
 435         (void) dev;
 436         return 1;
 437 }
 438
 439 struct display_info_t const displays[] = {{
 440         .bus    = -1,
 441         .addr   = 0,
 442         .pixfmt = IPU_PIX_FMT_RGB24,
 443         .detect = detect_hdmi,
 444         .enable = do_enable_hdmi,
 445         .mode   = {
 446                 .name           = "HDMI",
 447                 .refresh        = 60,
 448                 .xres           = 1024,
 449                 .yres           = 768,
 450                 .pixclock       = 15385,
 451                 .left_margin    = 220,
 452                 .right_margin   = 40,
 453                 .upper_margin   = 21,
 454                 .lower_margin   = 7,
 455                 .hsync_len      = 60,
 456                 .vsync_len      = 10,
 457                 .sync           = FB_SYNC_EXT,
 458                 .vmode          = FB_VMODE_NONINTERLACED
 459 } }, {
 460         .bus    = -1,
 461         .addr   = 0,
 462         .pixfmt = IPU_PIX_FMT_RGB666,
 463         .detect = detect_default,
 464         .enable = enable_rgb,
 465         .mode   = {
 466                 .name           = "vga-rgb",
 467                 .refresh        = 60,
 468                 .xres           = 640,
 469                 .yres           = 480,
 470                 .pixclock       = 33000,
 471                 .left_margin    = 48,
 472                 .right_margin   = 16,
 473                 .upper_margin   = 31,
 474                 .lower_margin   = 11,
 475                 .hsync_len      = 96,
 476                 .vsync_len      = 2,
 477                 .sync           = 0,
 478                 .vmode          = FB_VMODE_NONINTERLACED
 479 } }, {
 480         .bus    = -1,
 481         .addr   = 0,
 482         .pixfmt = IPU_PIX_FMT_RGB666,
 483         .enable = enable_rgb,
 484         .mode   = {
 485                 .name           = "wvga-rgb",
 486                 .refresh        = 60,
 487                 .xres           = 800,
 488                 .yres           = 480,
 489                 .pixclock       = 25000,
 490                 .left_margin    = 40,
 491                 .right_margin   = 88,
 492                 .upper_margin   = 33,
 493                 .lower_margin   = 10,
 494                 .hsync_len      = 128,
 495                 .vsync_len      = 2,
 496                 .sync           = 0,
 497                 .vmode          = FB_VMODE_NONINTERLACED
 498 } } };
 499 size_t display_count = ARRAY_SIZE(displays);
 500
 501 static void setup_display(void)
 502 {
 503         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 504         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 505         int reg;
 506
 507         enable_ipu_clock();
 508         imx_setup_hdmi();
 509         /* Turn on LDB0,IPU,IPU DI0 clocks */
 510         reg = __raw_readl(&mxc_ccm->CCGR3);
 511         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 512         writel(reg, &mxc_ccm->CCGR3);
 513
 514         /* set LDB0, LDB1 clk select to 011/011 */
 515         reg = readl(&mxc_ccm->cs2cdr);
 516         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 517                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 518         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 519               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 520         writel(reg, &mxc_ccm->cs2cdr);
 521
 522         reg = readl(&mxc_ccm->cscmr2);
 523         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 524         writel(reg, &mxc_ccm->cscmr2);
 525
 526         reg = readl(&mxc_ccm->chsccdr);
 527         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 528                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 529         writel(reg, &mxc_ccm->chsccdr);
 530
 531         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 532              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 533              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 534              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 535              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 536              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 537              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 538              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 539              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 540         writel(reg, &iomux->gpr[2]);
 541
 542         reg = readl(&iomux->gpr[3]);
 543         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 544                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 545             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 546                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 547         writel(reg, &iomux->gpr[3]);
 548
 549         /* backlight unconditionally on for now */
 550         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 551                                          ARRAY_SIZE(backlight_pads));
 552         /* use 0 for EDT 7", use 1 for LG fullHD panel */
 553         gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
 554         gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
 555         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
 556         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 557 }
 558
 559 /*
 560  * Backlight off before OS handover
 561  */
 562 void board_preboot_os(void)
 563 {
 564         gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
 565         gpio_direction_output(RGB_BACKLIGHT_GP, 0);
 566 }
 567 #endif /* defined(CONFIG_VIDEO_IPUV3) */
 568
 569 int board_early_init_f(void)
 570 {
 571         imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
 572                                          ARRAY_SIZE(pwr_intb_pads));
 573         setup_iomux_uart();
 574
 575         return 0;
 576 }
 577
 578 /*
 579  * Do not overwrite the console
 580  * Use always serial for U-Boot console
 581  */
 582 int overwrite_console(void)
 583 {
 584         return 1;
 585 }
 586
 587 int board_init(void)
 588 {
 589         /* address of boot parameters */
 590         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 591 #if defined(CONFIG_FEC_MXC)
 592         setup_fec();
 593 #endif
 594 #if defined(CONFIG_VIDEO_IPUV3)
 595         setup_display();
 596 #endif
 597
 598 #ifdef CONFIG_TDX_CMD_IMX_MFGR
 599         (void) pmic_init();
 600 #endif
 601
 602 #ifdef CONFIG_SATA
 603         setup_sata();
 604 #endif
 605
 606         setup_iomux_gpio();
 607
 608         return 0;
 609 }
 610
 611 #ifdef CONFIG_BOARD_LATE_INIT
 612 int board_late_init(void)
 613 {
 614 #if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 615         char env_str[256];
 616         u32 rev;
 617
 618         rev = get_board_revision();
 619         snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 620         env_set("board_rev", env_str);
 621 #endif
 622
 623 #ifdef CONFIG_CMD_USB_SDP
 624         if (is_boot_from_usb()) {
 625                 printf("Serial Downloader recovery mode, using sdp command\n");
 626                 env_set("bootdelay", "0");
 627                 env_set("bootcmd", "sdp 0");
 628         }
 629 #endif /* CONFIG_CMD_USB_SDP */
 630
 631         return 0;
 632 }
 633 #endif /* CONFIG_BOARD_LATE_INIT */
 634
 635 int checkboard(void)
 636 {
 637         char it[] = " IT";
 638         int minc, maxc;
 639
 640         switch (get_cpu_temp_grade(&minc, &maxc)) {
 641         case TEMP_AUTOMOTIVE:
 642         case TEMP_INDUSTRIAL:
 643                 break;
 644         case TEMP_EXTCOMMERCIAL:
 645         default:
 646                 it[0] = 0;
 647         };
 648         printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
 649                is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
 650                (gd->ram_size == 0x20000000) ? "512" : "256", it);
 651         return 0;
 652 }
 653
 654 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 655 int ft_board_setup(void *blob, struct bd_info *bd)
 656 {
 657         u32 cma_size;
 658
 659         ft_common_board_setup(blob, bd);
 660
 661         cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
 662         cma_size = min((u32)(gd->ram_size >> 1), cma_size);
 663
 664         fdt_setprop_u32(blob,
 665                         fdt_path_offset(blob, "/reserved-memory/linux,cma"),
 666                         "size",
 667                         cma_size);
 668         return 0;
 669 }
 670 #endif
 671
 672 #ifdef CONFIG_CMD_BMODE
 673 static const struct boot_mode board_boot_modes[] = {
 674         {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
 675         {NULL,  0},
 676 };
 677 #endif
 678
 679 int misc_init_r(void)
 680 {
 681 #ifdef CONFIG_CMD_BMODE
 682         add_board_boot_modes(board_boot_modes);
 683 #endif
 684         return 0;
 685 }
 686
 687 #ifdef CONFIG_LDO_BYPASS_CHECK
 688 /* TODO, use external pmic, for now always ldo_enable */
 689 void ldo_mode_set(int ldo_bypass)
 690 {
 691         return;
 692 }
 693 #endif
 694
 695 #ifdef CONFIG_SPL_BUILD
 696 #include <spl.h>
 697 #include <linux/libfdt.h>
 698 #include "asm/arch/mx6dl-ddr.h"
 699 #include "asm/arch/iomux.h"
 700 #include "asm/arch/crm_regs.h"
 701
 702 static int mx6s_dcd_table[] = {
 703 /* ddr-setup.cfg */
 704
 705 MX6_IOM_DRAM_SDQS0, 0x00000030,
 706 MX6_IOM_DRAM_SDQS1, 0x00000030,
 707 MX6_IOM_DRAM_SDQS2, 0x00000030,
 708 MX6_IOM_DRAM_SDQS3, 0x00000030,
 709 MX6_IOM_DRAM_SDQS4, 0x00000030,
 710 MX6_IOM_DRAM_SDQS5, 0x00000030,
 711 MX6_IOM_DRAM_SDQS6, 0x00000030,
 712 MX6_IOM_DRAM_SDQS7, 0x00000030,
 713
 714 MX6_IOM_GRP_B0DS, 0x00000030,
 715 MX6_IOM_GRP_B1DS, 0x00000030,
 716 MX6_IOM_GRP_B2DS, 0x00000030,
 717 MX6_IOM_GRP_B3DS, 0x00000030,
 718 MX6_IOM_GRP_B4DS, 0x00000030,
 719 MX6_IOM_GRP_B5DS, 0x00000030,
 720 MX6_IOM_GRP_B6DS, 0x00000030,
 721 MX6_IOM_GRP_B7DS, 0x00000030,
 722 MX6_IOM_GRP_ADDDS, 0x00000030,
 723 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 724 MX6_IOM_GRP_CTLDS, 0x00000030,
 725
 726 MX6_IOM_DRAM_DQM0, 0x00020030,
 727 MX6_IOM_DRAM_DQM1, 0x00020030,
 728 MX6_IOM_DRAM_DQM2, 0x00020030,
 729 MX6_IOM_DRAM_DQM3, 0x00020030,
 730 MX6_IOM_DRAM_DQM4, 0x00020030,
 731 MX6_IOM_DRAM_DQM5, 0x00020030,
 732 MX6_IOM_DRAM_DQM6, 0x00020030,
 733 MX6_IOM_DRAM_DQM7, 0x00020030,
 734
 735 MX6_IOM_DRAM_CAS, 0x00020030,
 736 MX6_IOM_DRAM_RAS, 0x00020030,
 737 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 738 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 739
 740 MX6_IOM_DRAM_RESET, 0x00020030,
 741 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 742 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 743
 744 MX6_IOM_DRAM_SDODT0, 0x00003030,
 745 MX6_IOM_DRAM_SDODT1, 0x00003030,
 746
 747 /* (differential input) */
 748 MX6_IOM_DDRMODE_CTL, 0x00020000,
 749 /* (differential input) */
 750 MX6_IOM_GRP_DDRMODE, 0x00020000,
 751 /* disable ddr pullups */
 752 MX6_IOM_GRP_DDRPKE, 0x00000000,
 753 MX6_IOM_DRAM_SDBA2, 0x00000000,
 754 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 755 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 756
 757 /* Read data DQ Byte0-3 delay */
 758 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 759 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 760 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 761 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 762 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 763 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 764 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 765 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 766
 767 /*
 768  * MDMISC       mirroring       interleaved (row/bank/col)
 769  */
 770 /* TODO: check what the RALAT field does */
 771 MX6_MMDC_P0_MDMISC, 0x00081740,
 772
 773 /*
 774  * MDSCR        con_req
 775  */
 776 MX6_MMDC_P0_MDSCR, 0x00008000,
 777
 778
 779 /* 800mhz_2x64mx16.cfg */
 780
 781 MX6_MMDC_P0_MDPDC, 0x0002002D,
 782 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 783 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 784 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 785 MX6_MMDC_P0_MDRWD, 0x000026D2,
 786 MX6_MMDC_P0_MDOR, 0x00301023,
 787 MX6_MMDC_P0_MDOTC, 0x00333030,
 788 MX6_MMDC_P0_MDPDC, 0x0002556D,
 789 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 790 MX6_MMDC_P0_MDASP, 0x00000017,
 791 /* DDR3 DATA BUS SIZE: 64BIT */
 792 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
 793 /* DDR3 DATA BUS SIZE: 32BIT */
 794 MX6_MMDC_P0_MDCTL, 0x82190000,
 795
 796 /* Write commands to DDR */
 797 /* Load Mode Registers */
 798 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 799 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 800 MX6_MMDC_P0_MDSCR, 0x04008032,
 801 MX6_MMDC_P0_MDSCR, 0x00008033,
 802 MX6_MMDC_P0_MDSCR, 0x00048031,
 803 MX6_MMDC_P0_MDSCR, 0x13208030,
 804 /* ZQ calibration */
 805 MX6_MMDC_P0_MDSCR, 0x04008040,
 806
 807 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 808 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 809 MX6_MMDC_P0_MDREF, 0x00005800,
 810
 811 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 812 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 813
 814 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 815 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 816 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 817 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 818
 819 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 820 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 821 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 822 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 823
 824 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 825 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 826 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 827 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 828
 829 MX6_MMDC_P0_MPMUR0, 0x00000800,
 830 MX6_MMDC_P1_MPMUR0, 0x00000800,
 831 MX6_MMDC_P0_MDSCR, 0x00000000,
 832 MX6_MMDC_P0_MAPSR, 0x00011006,
 833 };
 834
 835 static int mx6dl_dcd_table[] = {
 836 /* ddr-setup.cfg */
 837
 838 MX6_IOM_DRAM_SDQS0, 0x00000030,
 839 MX6_IOM_DRAM_SDQS1, 0x00000030,
 840 MX6_IOM_DRAM_SDQS2, 0x00000030,
 841 MX6_IOM_DRAM_SDQS3, 0x00000030,
 842 MX6_IOM_DRAM_SDQS4, 0x00000030,
 843 MX6_IOM_DRAM_SDQS5, 0x00000030,
 844 MX6_IOM_DRAM_SDQS6, 0x00000030,
 845 MX6_IOM_DRAM_SDQS7, 0x00000030,
 846
 847 MX6_IOM_GRP_B0DS, 0x00000030,
 848 MX6_IOM_GRP_B1DS, 0x00000030,
 849 MX6_IOM_GRP_B2DS, 0x00000030,
 850 MX6_IOM_GRP_B3DS, 0x00000030,
 851 MX6_IOM_GRP_B4DS, 0x00000030,
 852 MX6_IOM_GRP_B5DS, 0x00000030,
 853 MX6_IOM_GRP_B6DS, 0x00000030,
 854 MX6_IOM_GRP_B7DS, 0x00000030,
 855 MX6_IOM_GRP_ADDDS, 0x00000030,
 856 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 857 MX6_IOM_GRP_CTLDS, 0x00000030,
 858
 859 MX6_IOM_DRAM_DQM0, 0x00020030,
 860 MX6_IOM_DRAM_DQM1, 0x00020030,
 861 MX6_IOM_DRAM_DQM2, 0x00020030,
 862 MX6_IOM_DRAM_DQM3, 0x00020030,
 863 MX6_IOM_DRAM_DQM4, 0x00020030,
 864 MX6_IOM_DRAM_DQM5, 0x00020030,
 865 MX6_IOM_DRAM_DQM6, 0x00020030,
 866 MX6_IOM_DRAM_DQM7, 0x00020030,
 867
 868 MX6_IOM_DRAM_CAS, 0x00020030,
 869 MX6_IOM_DRAM_RAS, 0x00020030,
 870 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
 871 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
 872
 873 MX6_IOM_DRAM_RESET, 0x00020030,
 874 MX6_IOM_DRAM_SDCKE0, 0x00003000,
 875 MX6_IOM_DRAM_SDCKE1, 0x00003000,
 876
 877 MX6_IOM_DRAM_SDODT0, 0x00003030,
 878 MX6_IOM_DRAM_SDODT1, 0x00003030,
 879
 880 /* (differential input) */
 881 MX6_IOM_DDRMODE_CTL, 0x00020000,
 882 /* (differential input) */
 883 MX6_IOM_GRP_DDRMODE, 0x00020000,
 884 /* disable ddr pullups */
 885 MX6_IOM_GRP_DDRPKE, 0x00000000,
 886 MX6_IOM_DRAM_SDBA2, 0x00000000,
 887 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
 888 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
 889
 890 /* Read data DQ Byte0-3 delay */
 891 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
 892 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
 893 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
 894 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
 895 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
 896 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
 897 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
 898 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
 899
 900 /*
 901  * MDMISC       mirroring       interleaved (row/bank/col)
 902  */
 903 /* TODO: check what the RALAT field does */
 904 MX6_MMDC_P0_MDMISC, 0x00081740,
 905
 906 /*
 907  * MDSCR        con_req
 908  */
 909 MX6_MMDC_P0_MDSCR, 0x00008000,
 910
 911
 912 /* 800mhz_2x64mx16.cfg */
 913
 914 MX6_MMDC_P0_MDPDC, 0x0002002D,
 915 MX6_MMDC_P0_MDCFG0, 0x2C305503,
 916 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
 917 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
 918 MX6_MMDC_P0_MDRWD, 0x000026D2,
 919 MX6_MMDC_P0_MDOR, 0x00301023,
 920 MX6_MMDC_P0_MDOTC, 0x00333030,
 921 MX6_MMDC_P0_MDPDC, 0x0002556D,
 922 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
 923 MX6_MMDC_P0_MDASP, 0x00000017,
 924 /* DDR3 DATA BUS SIZE: 64BIT */
 925 MX6_MMDC_P0_MDCTL, 0x821A0000,
 926 /* DDR3 DATA BUS SIZE: 32BIT */
 927 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
 928
 929 /* Write commands to DDR */
 930 /* Load Mode Registers */
 931 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
 932 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
 933 MX6_MMDC_P0_MDSCR, 0x04008032,
 934 MX6_MMDC_P0_MDSCR, 0x00008033,
 935 MX6_MMDC_P0_MDSCR, 0x00048031,
 936 MX6_MMDC_P0_MDSCR, 0x13208030,
 937 /* ZQ calibration */
 938 MX6_MMDC_P0_MDSCR, 0x04008040,
 939
 940 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
 941 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
 942 MX6_MMDC_P0_MDREF, 0x00005800,
 943
 944 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
 945 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
 946
 947 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
 948 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
 949 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
 950 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
 951
 952 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
 953 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
 954 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
 955 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
 956
 957 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
 958 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
 959 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
 960 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
 961
 962 MX6_MMDC_P0_MPMUR0, 0x00000800,
 963 MX6_MMDC_P1_MPMUR0, 0x00000800,
 964 MX6_MMDC_P0_MDSCR, 0x00000000,
 965 MX6_MMDC_P0_MAPSR, 0x00011006,
 966 };
 967
 968 static void ccgr_init(void)
 969 {
 970         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 971
 972         writel(0x00C03F3F, &ccm->CCGR0);
 973         writel(0x0030FC03, &ccm->CCGR1);
 974         writel(0x0FFFFFF3, &ccm->CCGR2);
 975         writel(0x3FF0300F, &ccm->CCGR3);
 976         writel(0x00FFF300, &ccm->CCGR4);
 977         writel(0x0F0000F3, &ccm->CCGR5);
 978         writel(0x000003FF, &ccm->CCGR6);
 979
 980 /*
 981  * Setup CCM_CCOSR register as follows:
 982  *
 983  * clko2_en  = 1     --> CKO2 enabled
 984  * clko2_div = 000   --> divide by 1
 985  * clko2_sel = 01110 --> osc_clk (24MHz)
 986  *
 987  * clk_out_sel = 1   --> Output CKO2 to CKO1
 988  *
 989  * This sets both CLKO2/CLKO1 output to 24MHz,
 990  * CLKO1 configuration not relevant because of clk_out_sel
 991  * (CLKO1 set to default)
 992  */
 993         writel(0x010E0101, &ccm->ccosr);
 994 }
 995
 996 static void ddr_init(int *table, int size)
 997 {
 998         int i;
 999
1000         for (i = 0; i < size / 2 ; i++)
1001                 writel(table[2 * i + 1], table[2 * i]);
1002 }
1003
1004 /* Perform DDR DRAM calibration */
1005 static void spl_dram_perform_cal(u8 dsize)
1006 {
1007 #ifdef CONFIG_MX6_DDRCAL
1008         int err;
1009         struct mx6_ddr_sysinfo ddr_sysinfo = {
1010                 .dsize = dsize,
1011         };
1012
1013         err = mmdc_do_write_level_calibration(&ddr_sysinfo);
1014         if (err)
1015                 printf("error %d from write level calibration\n", err);
1016         err = mmdc_do_dqs_calibration(&ddr_sysinfo);
1017         if (err)
1018                 printf("error %d from dqs calibration\n", err);
1019 #endif
1020 }
1021
1022 static void spl_dram_init(void)
1023 {
1024         int minc, maxc;
1025         u8 dsize = 2;
1026
1027         switch (get_cpu_temp_grade(&minc, &maxc)) {
1028         case TEMP_COMMERCIAL:
1029         case TEMP_EXTCOMMERCIAL:
1030                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1031                         puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1032                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1033                 } else {
1034                         puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1035                         dsize = 1;
1036                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1037                 }
1038                 break;
1039         case TEMP_INDUSTRIAL:
1040         case TEMP_AUTOMOTIVE:
1041         default:
1042                 if (is_cpu_type(MXC_CPU_MX6DL)) {
1043                         puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
1044                         ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1045                 } else {
1046                         puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1047                         dsize = 1;
1048                         ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1049                 }
1050                 break;
1051         };
1052         udelay(100);
1053         spl_dram_perform_cal(dsize);
1054 }
1055
1056 static iomux_v3_cfg_t const gpio_reset_pad[] = {
1057         MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
1058                                         MUX_MODE_SION
1059 #define GPIO_NRESET IMX_GPIO_NR(6, 27)
1060 };
1061
1062 #define IMX_RESET_CAUSE_POR 0x00011
1063 static void nreset_out(void)
1064 {
1065         int reset_cause = get_imx_reset_cause();
1066
1067         if (reset_cause != IMX_RESET_CAUSE_POR) {
1068                 imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
1069                                                  ARRAY_SIZE(gpio_reset_pad));
1070                 gpio_direction_output(GPIO_NRESET, 1);
1071                 udelay(100);
1072                 gpio_direction_output(GPIO_NRESET, 0);
1073         }
1074 }
1075
1076 void board_init_f(ulong dummy)
1077 {
1078         /* setup AIPS and disable watchdog */
1079         arch_cpu_init();
1080
1081         ccgr_init();
1082         gpr_init();
1083
1084         /* iomux */
1085         board_early_init_f();
1086
1087         /* setup GP timer */
1088         timer_init();
1089
1090         /* UART clocks enabled and gd valid - init serial console */
1091         preloader_console_init();
1092
1093         /* Make sure we use dte mode */
1094         setup_dtemode_uart();
1095
1096         /* DDR initialization */
1097         spl_dram_init();
1098
1099         /* Clear the BSS. */
1100         memset(__bss_start, 0, __bss_end - __bss_start);
1101
1102         /* Assert nReset_Out */
1103         nreset_out();
1104
1105         /* load/boot image from boot device */
1106         board_init_r(NULL, 0);
1107 }
1108
1109 #ifdef CONFIG_SPL_LOAD_FIT
1110 int board_fit_config_name_match(const char *name)
1111 {
1112         if (!strcmp(name, "imx6-colibri"))
1113                 return 0;
1114
1115         return -1;
1116 }
1117 #endif
1118
1119 void reset_cpu(void)
1120 {
1121 }
1122
1123 #endif /* CONFIG_SPL_BUILD */
1124
1125 static struct mxc_serial_plat mxc_serial_plat = {
1126         .reg = (struct mxc_uart *)UART1_BASE,
1127         .use_dte = true,
1128 };
1129
1130 U_BOOT_DRVINFO(mxc_serial) = {
1131         .name = "serial_mxc",
1132         .plat = &mxc_serial_plat,
1133 };