board/ti/ks2_evm/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Keystone : Board initialization
   4  *
   5  * (C) Copyright 2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include "board.h"
  11 #include <env.h>
  12 #include <spl.h>
  13 #include <exports.h>
  14 #include <fdt_support.h>
  15 #include <asm/arch/ddr3.h>
  16 #include <asm/arch/psc_defs.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/ti-common/ti-aemif.h>
  19 #include <asm/ti-common/keystone_net.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #if defined(CONFIG_TI_AEMIF)
  24 static struct aemif_config aemif_configs[] = {
  25         {                       /* CS0 */
  26                 .mode           = AEMIF_MODE_NAND,
  27                 .wr_setup       = 0xf,
  28                 .wr_strobe      = 0x3f,
  29                 .wr_hold        = 7,
  30                 .rd_setup       = 0xf,
  31                 .rd_strobe      = 0x3f,
  32                 .rd_hold        = 7,
  33                 .turn_around    = 3,
  34                 .width          = AEMIF_WIDTH_8,
  35         },
  36 };
  37 #endif
  38
  39 int dram_init(void)
  40 {
  41         u32 ddr3_size;
  42
  43         ddr3_size = ddr3_init();
  44
  45         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  46                                     CONFIG_MAX_RAM_BANK_SIZE);
  47 #if defined(CONFIG_TI_AEMIF)
  48         if (!board_is_k2g_ice())
  49                 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  50 #endif
  51
  52         if (!board_is_k2g_ice()) {
  53                 if (ddr3_size)
  54                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
  55                 else
  56                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
  57                                       gd->ram_size >> 30);
  58         }
  59
  60         return 0;
  61 }
  62
  63 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
  64 {
  65         return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
  66 }
  67
  68 int board_init(void)
  69 {
  70         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  71         return 0;
  72 }
  73
  74 #ifdef CONFIG_SPL_BUILD
  75 void spl_board_init(void)
  76 {
  77         spl_init_keystone_plls();
  78         preloader_console_init();
  79 }
  80
  81 u32 spl_boot_device(void)
  82 {
  83 #if defined(CONFIG_SPL_SPI_LOAD)
  84         return BOOT_DEVICE_SPI;
  85 #else
  86         puts("Unknown boot device\n");
  87         hang();
  88 #endif
  89 }
  90 #endif
  91
  92 #ifdef CONFIG_OF_BOARD_SETUP
  93 int ft_board_setup(void *blob, bd_t *bd)
  94 {
  95         int lpae;
  96         char *env;
  97         char *endp;
  98         int nbanks;
  99         u64 size[2];
 100         u64 start[2];
 101         u32 ddr3a_size;
 102
 103         env = env_get("mem_lpae");
 104         lpae = env && simple_strtol(env, NULL, 0);
 105
 106         ddr3a_size = 0;
 107         if (lpae) {
 108                 ddr3a_size = ddr3_get_size();
 109                 if ((ddr3a_size != 8) && (ddr3a_size != 4))
 110                         ddr3a_size = 0;
 111         }
 112
 113         nbanks = 1;
 114         start[0] = bd->bi_dram[0].start;
 115         size[0]  = bd->bi_dram[0].size;
 116
 117         /* adjust memory start address for LPAE */
 118         if (lpae) {
 119                 start[0] -= CONFIG_SYS_SDRAM_BASE;
 120                 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 121         }
 122
 123         if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
 124                 size[1] = ((u64)ddr3a_size - 2) << 30;
 125                 start[1] = 0x880000000;
 126                 nbanks++;
 127         }
 128
 129         /* reserve memory at start of bank */
 130         env = env_get("mem_reserve_head");
 131         if (env) {
 132                 start[0] += ustrtoul(env, &endp, 0);
 133                 size[0] -= ustrtoul(env, &endp, 0);
 134         }
 135
 136         env = env_get("mem_reserve");
 137         if (env)
 138                 size[0] -= ustrtoul(env, &endp, 0);
 139
 140         fdt_fixup_memory_banks(blob, start, size, nbanks);
 141
 142         return 0;
 143 }
 144
 145 void ft_board_setup_ex(void *blob, bd_t *bd)
 146 {
 147         int lpae;
 148         u64 size;
 149         char *env;
 150         u64 *reserve_start;
 151         int unitrd_fixup = 0;
 152
 153         env = env_get("mem_lpae");
 154         lpae = env && simple_strtol(env, NULL, 0);
 155         env = env_get("uinitrd_fixup");
 156         unitrd_fixup = env && simple_strtol(env, NULL, 0);
 157
 158         /* Fix up the initrd */
 159         if (lpae && unitrd_fixup) {
 160                 int nodeoffset;
 161                 int err;
 162                 u64 *prop1, *prop2;
 163                 u64 initrd_start, initrd_end;
 164
 165                 nodeoffset = fdt_path_offset(blob, "/chosen");
 166                 if (nodeoffset >= 0) {
 167                         prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
 168                                             "linux,initrd-start", NULL);
 169                         prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
 170                                             "linux,initrd-end", NULL);
 171                         if (prop1 && prop2) {
 172                                 initrd_start = __be64_to_cpu(*prop1);
 173                                 initrd_start -= CONFIG_SYS_SDRAM_BASE;
 174                                 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 175                                 initrd_start = __cpu_to_be64(initrd_start);
 176                                 initrd_end = __be64_to_cpu(*prop2);
 177                                 initrd_end -= CONFIG_SYS_SDRAM_BASE;
 178                                 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 179                                 initrd_end = __cpu_to_be64(initrd_end);
 180
 181                                 err = fdt_delprop(blob, nodeoffset,
 182                                                   "linux,initrd-start");
 183                                 if (err < 0)
 184                                         puts("error deleting initrd-start\n");
 185
 186                                 err = fdt_delprop(blob, nodeoffset,
 187                                                   "linux,initrd-end");
 188                                 if (err < 0)
 189                                         puts("error deleting initrd-end\n");
 190
 191                                 err = fdt_setprop(blob, nodeoffset,
 192                                                   "linux,initrd-start",
 193                                                   &initrd_start,
 194                                                   sizeof(initrd_start));
 195                                 if (err < 0)
 196                                         puts("error adding initrd-start\n");
 197
 198                                 err = fdt_setprop(blob, nodeoffset,
 199                                                   "linux,initrd-end",
 200                                                   &initrd_end,
 201                                                   sizeof(initrd_end));
 202                                 if (err < 0)
 203                                         puts("error adding linux,initrd-end\n");
 204                         }
 205                 }
 206         }
 207
 208         if (lpae) {
 209                 /*
 210                  * the initrd and other reserved memory areas are
 211                  * embedded in in the DTB itslef. fix up these addresses
 212                  * to 36 bit format
 213                  */
 214                 reserve_start = (u64 *)((char *)blob +
 215                                        fdt_off_mem_rsvmap(blob));
 216                 while (1) {
 217                         *reserve_start = __cpu_to_be64(*reserve_start);
 218                         size = __cpu_to_be64(*(reserve_start + 1));
 219                         if (size) {
 220                                 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
 221                                 *reserve_start +=
 222                                         CONFIG_SYS_LPAE_SDRAM_BASE;
 223                                 *reserve_start =
 224                                         __cpu_to_be64(*reserve_start);
 225                         } else {
 226                                 break;
 227                         }
 228                         reserve_start += 2;
 229                 }
 230         }
 231
 232         ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 233 }
 234 #endif /* CONFIG_OF_BOARD_SETUP */
 235
 236 #if defined(CONFIG_DTB_RESELECT)
 237 int __weak embedded_dtb_select(void)
 238 {
 239         return 0;
 240 }
 241 #endif