board/ti/ks2_evm/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Keystone : Board initialization
   4  *
   5  * (C) Copyright 2014
   6  *     Texas Instruments Incorporated, <www.ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include "board.h"
  11 #include <env.h>
  12 #include <hang.h>
  13 #include <init.h>
  14 #include <spl.h>
  15 #include <exports.h>
  16 #include <fdt_support.h>
  17 #include <asm/arch/ddr3.h>
  18 #include <asm/arch/psc_defs.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/ti-common/ti-aemif.h>
  21 #include <asm/ti-common/keystone_net.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #if defined(CONFIG_TI_AEMIF)
  26 static struct aemif_config aemif_configs[] = {
  27         {                       /* CS0 */
  28                 .mode           = AEMIF_MODE_NAND,
  29                 .wr_setup       = 0xf,
  30                 .wr_strobe      = 0x3f,
  31                 .wr_hold        = 7,
  32                 .rd_setup       = 0xf,
  33                 .rd_strobe      = 0x3f,
  34                 .rd_hold        = 7,
  35                 .turn_around    = 3,
  36                 .width          = AEMIF_WIDTH_8,
  37         },
  38 };
  39 #endif
  40
  41 int dram_init(void)
  42 {
  43         u32 ddr3_size;
  44
  45         ddr3_size = ddr3_init();
  46
  47         gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  48                                     CONFIG_MAX_RAM_BANK_SIZE);
  49 #if defined(CONFIG_TI_AEMIF)
  50         if (!board_is_k2g_ice())
  51                 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
  52 #endif
  53
  54         if (!board_is_k2g_ice()) {
  55                 if (ddr3_size)
  56                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
  57                 else
  58                         ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
  59                                       gd->ram_size >> 30);
  60         }
  61
  62         return 0;
  63 }
  64
  65 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
  66 {
  67         return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
  68 }
  69
  70 int board_init(void)
  71 {
  72         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  73         return 0;
  74 }
  75
  76 #ifdef CONFIG_SPL_BUILD
  77 void spl_board_init(void)
  78 {
  79         spl_init_keystone_plls();
  80         preloader_console_init();
  81 }
  82
  83 u32 spl_boot_device(void)
  84 {
  85 #if defined(CONFIG_SPL_SPI_LOAD)
  86         return BOOT_DEVICE_SPI;
  87 #else
  88         puts("Unknown boot device\n");
  89         hang();
  90 #endif
  91 }
  92 #endif
  93
  94 #ifdef CONFIG_OF_BOARD_SETUP
  95 int ft_board_setup(void *blob, bd_t *bd)
  96 {
  97         int lpae;
  98         char *env;
  99         char *endp;
 100         int nbanks;
 101         u64 size[2];
 102         u64 start[2];
 103         u32 ddr3a_size;
 104
 105         env = env_get("mem_lpae");
 106         lpae = env && simple_strtol(env, NULL, 0);
 107
 108         ddr3a_size = 0;
 109         if (lpae) {
 110                 ddr3a_size = ddr3_get_size();
 111                 if ((ddr3a_size != 8) && (ddr3a_size != 4))
 112                         ddr3a_size = 0;
 113         }
 114
 115         nbanks = 1;
 116         start[0] = bd->bi_dram[0].start;
 117         size[0]  = bd->bi_dram[0].size;
 118
 119         /* adjust memory start address for LPAE */
 120         if (lpae) {
 121                 start[0] -= CONFIG_SYS_SDRAM_BASE;
 122                 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
 123         }
 124
 125         if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
 126                 size[1] = ((u64)ddr3a_size - 2) << 30;
 127                 start[1] = 0x880000000;
 128                 nbanks++;
 129         }
 130
 131         /* reserve memory at start of bank */
 132         env = env_get("mem_reserve_head");
 133         if (env) {
 134                 start[0] += ustrtoul(env, &endp, 0);
 135                 size[0] -= ustrtoul(env, &endp, 0);
 136         }
 137
 138         env = env_get("mem_reserve");
 139         if (env)
 140                 size[0] -= ustrtoul(env, &endp, 0);
 141
 142         fdt_fixup_memory_banks(blob, start, size, nbanks);
 143
 144         return 0;
 145 }
 146
 147 void ft_board_setup_ex(void *blob, bd_t *bd)
 148 {
 149         int lpae;
 150         u64 size;
 151         char *env;
 152         u64 *reserve_start;
 153         int unitrd_fixup = 0;
 154
 155         env = env_get("mem_lpae");
 156         lpae = env && simple_strtol(env, NULL, 0);
 157         env = env_get("uinitrd_fixup");
 158         unitrd_fixup = env && simple_strtol(env, NULL, 0);
 159
 160         /* Fix up the initrd */
 161         if (lpae && unitrd_fixup) {
 162                 int nodeoffset;
 163                 int err;
 164                 u64 *prop1, *prop2;
 165                 u64 initrd_start, initrd_end;
 166
 167                 nodeoffset = fdt_path_offset(blob, "/chosen");
 168                 if (nodeoffset >= 0) {
 169                         prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
 170                                             "linux,initrd-start", NULL);
 171                         prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
 172                                             "linux,initrd-end", NULL);
 173                         if (prop1 && prop2) {
 174                                 initrd_start = __be64_to_cpu(*prop1);
 175                                 initrd_start -= CONFIG_SYS_SDRAM_BASE;
 176                                 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
 177                                 initrd_start = __cpu_to_be64(initrd_start);
 178                                 initrd_end = __be64_to_cpu(*prop2);
 179                                 initrd_end -= CONFIG_SYS_SDRAM_BASE;
 180                                 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
 181                                 initrd_end = __cpu_to_be64(initrd_end);
 182
 183                                 err = fdt_delprop(blob, nodeoffset,
 184                                                   "linux,initrd-start");
 185                                 if (err < 0)
 186                                         puts("error deleting initrd-start\n");
 187
 188                                 err = fdt_delprop(blob, nodeoffset,
 189                                                   "linux,initrd-end");
 190                                 if (err < 0)
 191                                         puts("error deleting initrd-end\n");
 192
 193                                 err = fdt_setprop(blob, nodeoffset,
 194                                                   "linux,initrd-start",
 195                                                   &initrd_start,
 196                                                   sizeof(initrd_start));
 197                                 if (err < 0)
 198                                         puts("error adding initrd-start\n");
 199
 200                                 err = fdt_setprop(blob, nodeoffset,
 201                                                   "linux,initrd-end",
 202                                                   &initrd_end,
 203                                                   sizeof(initrd_end));
 204                                 if (err < 0)
 205                                         puts("error adding linux,initrd-end\n");
 206                         }
 207                 }
 208         }
 209
 210         if (lpae) {
 211                 /*
 212                  * the initrd and other reserved memory areas are
 213                  * embedded in in the DTB itslef. fix up these addresses
 214                  * to 36 bit format
 215                  */
 216                 reserve_start = (u64 *)((char *)blob +
 217                                        fdt_off_mem_rsvmap(blob));
 218                 while (1) {
 219                         *reserve_start = __cpu_to_be64(*reserve_start);
 220                         size = __cpu_to_be64(*(reserve_start + 1));
 221                         if (size) {
 222                                 *reserve_start -= CONFIG_SYS_SDRAM_BASE;
 223                                 *reserve_start +=
 224                                         CONFIG_SYS_LPAE_SDRAM_BASE;
 225                                 *reserve_start =
 226                                         __cpu_to_be64(*reserve_start);
 227                         } else {
 228                                 break;
 229                         }
 230                         reserve_start += 2;
 231                 }
 232         }
 233
 234         ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 235 }
 236 #endif /* CONFIG_OF_BOARD_SETUP */
 237
 238 #if defined(CONFIG_DTB_RESELECT)
 239 int __weak embedded_dtb_select(void)
 240 {
 241         return 0;
 242 }
 243 #endif