board/ti/am335x/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for TI AM335X based boards
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <env.h>
  13 #include <errno.h>
  14 #include <image.h>
  15 #include <init.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <spl.h>
  19 #include <serial.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/omap.h>
  23 #include <asm/arch/ddr_defs.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/clk_synthesizer.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/mmc_host_def.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <asm/arch/mem.h>
  30 #include <asm/global_data.h>
  31 #include <asm/io.h>
  32 #include <asm/emif.h>
  33 #include <asm/gpio.h>
  34 #include <asm/omap_common.h>
  35 #include <asm/omap_sec_common.h>
  36 #include <asm/omap_mmc.h>
  37 #include <i2c.h>
  38 #include <miiphy.h>
  39 #include <cpsw.h>
  40 #include <linux/bitops.h>
  41 #include <linux/delay.h>
  42 #include <power/tps65217.h>
  43 #include <power/tps65910.h>
  44 #include <env_internal.h>
  45 #include <watchdog.h>
  46 #include "../common/board_detect.h"
  47 #include "../common/cape_detect.h"
  48 #include "board.h"
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 /* GPIO that controls power to DDR on EVM-SK */
  53 #define GPIO_TO_PIN(bank, gpio)         (32 * (bank) + (gpio))
  54 #define GPIO_DDR_VTT_EN         GPIO_TO_PIN(0, 7)
  55 #define ICE_GPIO_DDR_VTT_EN     GPIO_TO_PIN(0, 18)
  56 #define GPIO_PR1_MII_CTRL       GPIO_TO_PIN(3, 4)
  57 #define GPIO_MUX_MII_CTRL       GPIO_TO_PIN(3, 10)
  58 #define GPIO_FET_SWITCH_CTRL    GPIO_TO_PIN(0, 7)
  59 #define GPIO_PHY_RESET          GPIO_TO_PIN(2, 5)
  60 #define GPIO_ETH0_MODE          GPIO_TO_PIN(0, 11)
  61 #define GPIO_ETH1_MODE          GPIO_TO_PIN(1, 26)
  62
  63 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  64
  65 #define GPIO0_RISINGDETECT      (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  66 #define GPIO1_RISINGDETECT      (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  67
  68 #define GPIO0_IRQSTATUS1        (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  69 #define GPIO1_IRQSTATUS1        (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  70
  71 #define GPIO0_IRQSTATUSRAW      (AM33XX_GPIO0_BASE + 0x024)
  72 #define GPIO1_IRQSTATUSRAW      (AM33XX_GPIO1_BASE + 0x024)
  73
  74 /*
  75  * Read header information from EEPROM into global structure.
  76  */
  77 #ifdef CONFIG_TI_I2C_BOARD_DETECT
  78 void do_board_detect(void)
  79 {
  80         enable_i2c0_pin_mux();
  81         enable_i2c2_pin_mux();
  82         if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  83                                  CONFIG_EEPROM_CHIP_ADDRESS))
  84                 printf("ti_i2c_eeprom_init failed\n");
  85 }
  86 #endif
  87
  88 #ifndef CONFIG_DM_SERIAL
  89 struct serial_device *default_serial_console(void)
  90 {
  91         if (board_is_icev2())
  92                 return &eserial4_device;
  93         else
  94                 return &eserial1_device;
  95 }
  96 #endif
  97
  98 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  99 static const struct ddr_data ddr2_data = {
 100         .datardsratio0 = MT47H128M16RT25E_RD_DQS,
 101         .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
 102         .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 103 };
 104
 105 static const struct cmd_control ddr2_cmd_ctrl_data = {
 106         .cmd0csratio = MT47H128M16RT25E_RATIO,
 107
 108         .cmd1csratio = MT47H128M16RT25E_RATIO,
 109
 110         .cmd2csratio = MT47H128M16RT25E_RATIO,
 111 };
 112
 113 static const struct emif_regs ddr2_emif_reg_data = {
 114         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 115         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 116         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 117         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 118         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 119         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 120 };
 121
 122 static const struct emif_regs ddr2_evm_emif_reg_data = {
 123         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 124         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 125         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 126         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 127         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 128         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 129         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 130 };
 131
 132 static const struct ddr_data ddr3_data = {
 133         .datardsratio0 = MT41J128MJT125_RD_DQS,
 134         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 135         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 136         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 137 };
 138
 139 static const struct ddr_data ddr3_beagleblack_data = {
 140         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 141         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 142         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 143         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 144 };
 145
 146 static const struct ddr_data ddr3_evm_data = {
 147         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 148         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 149         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 150         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 151 };
 152
 153 static const struct ddr_data ddr3_icev2_data = {
 154         .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
 155         .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
 156         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
 157         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
 158 };
 159
 160 static const struct cmd_control ddr3_cmd_ctrl_data = {
 161         .cmd0csratio = MT41J128MJT125_RATIO,
 162         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 163
 164         .cmd1csratio = MT41J128MJT125_RATIO,
 165         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 166
 167         .cmd2csratio = MT41J128MJT125_RATIO,
 168         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 169 };
 170
 171 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 172         .cmd0csratio = MT41K256M16HA125E_RATIO,
 173         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 174
 175         .cmd1csratio = MT41K256M16HA125E_RATIO,
 176         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 177
 178         .cmd2csratio = MT41K256M16HA125E_RATIO,
 179         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 180 };
 181
 182 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 183         .cmd0csratio = MT41J512M8RH125_RATIO,
 184         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 185
 186         .cmd1csratio = MT41J512M8RH125_RATIO,
 187         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 188
 189         .cmd2csratio = MT41J512M8RH125_RATIO,
 190         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 191 };
 192
 193 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
 194         .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
 195         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 196
 197         .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
 198         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 199
 200         .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
 201         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
 202 };
 203
 204 static struct emif_regs ddr3_emif_reg_data = {
 205         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 206         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 207         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 208         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 209         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 210         .zq_config = MT41J128MJT125_ZQ_CFG,
 211         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 212                                 PHY_EN_DYN_PWRDN,
 213 };
 214
 215 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 216         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 217         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 218         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 219         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 220         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 221         .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 222         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 223         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 224 };
 225
 226 static struct emif_regs ddr3_evm_emif_reg_data = {
 227         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 228         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 229         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 230         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 231         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 232         .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 233         .zq_config = MT41J512M8RH125_ZQ_CFG,
 234         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 235                                 PHY_EN_DYN_PWRDN,
 236 };
 237
 238 static struct emif_regs ddr3_icev2_emif_reg_data = {
 239         .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
 240         .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
 241         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
 242         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
 243         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
 244         .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
 245         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
 246                                 PHY_EN_DYN_PWRDN,
 247 };
 248
 249 #ifdef CONFIG_SPL_OS_BOOT
 250 int spl_start_uboot(void)
 251 {
 252 #ifdef CONFIG_SPL_SERIAL_SUPPORT
 253         /* break into full u-boot on 'c' */
 254         if (serial_tstc() && serial_getc() == 'c')
 255                 return 1;
 256 #endif
 257
 258 #ifdef CONFIG_SPL_ENV_SUPPORT
 259         env_init();
 260         env_load();
 261         if (env_get_yesno("boot_os") != 1)
 262                 return 1;
 263 #endif
 264
 265         return 0;
 266 }
 267 #endif
 268
 269 const struct dpll_params *get_dpll_ddr_params(void)
 270 {
 271         int ind = get_sys_clk_index();
 272
 273         if (board_is_evm_sk())
 274                 return &dpll_ddr3_303MHz[ind];
 275         else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
 276                 return &dpll_ddr3_400MHz[ind];
 277         else if (board_is_evm_15_or_later())
 278                 return &dpll_ddr3_303MHz[ind];
 279         else
 280                 return &dpll_ddr2_266MHz[ind];
 281 }
 282
 283 static u8 bone_not_connected_to_ac_power(void)
 284 {
 285         if (board_is_bone()) {
 286                 uchar pmic_status_reg;
 287                 if (tps65217_reg_read(TPS65217_STATUS,
 288                                       &pmic_status_reg))
 289                         return 1;
 290                 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 291                         puts("No AC power, switching to default OPP\n");
 292                         return 1;
 293                 }
 294         }
 295         return 0;
 296 }
 297
 298 const struct dpll_params *get_dpll_mpu_params(void)
 299 {
 300         int ind = get_sys_clk_index();
 301         int freq = am335x_get_efuse_mpu_max_freq(cdev);
 302
 303         if (bone_not_connected_to_ac_power())
 304                 freq = MPUPLL_M_600;
 305
 306         if (board_is_pb() || board_is_bone_lt())
 307                 freq = MPUPLL_M_1000;
 308
 309         switch (freq) {
 310         case MPUPLL_M_1000:
 311                 return &dpll_mpu_opp[ind][5];
 312         case MPUPLL_M_800:
 313                 return &dpll_mpu_opp[ind][4];
 314         case MPUPLL_M_720:
 315                 return &dpll_mpu_opp[ind][3];
 316         case MPUPLL_M_600:
 317                 return &dpll_mpu_opp[ind][2];
 318         case MPUPLL_M_500:
 319                 return &dpll_mpu_opp100;
 320         case MPUPLL_M_300:
 321                 return &dpll_mpu_opp[ind][0];
 322         }
 323
 324         return &dpll_mpu_opp[ind][0];
 325 }
 326
 327 static void scale_vcores_bone(int freq)
 328 {
 329         int usb_cur_lim, mpu_vdd;
 330
 331         /*
 332          * Only perform PMIC configurations if board rev > A1
 333          * on Beaglebone White
 334          */
 335         if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
 336                 return;
 337
 338         if (power_tps65217_init(0))
 339                 return;
 340
 341
 342         /*
 343          * On Beaglebone White we need to ensure we have AC power
 344          * before increasing the frequency.
 345          */
 346         if (bone_not_connected_to_ac_power())
 347                 freq = MPUPLL_M_600;
 348
 349         /*
 350          * Override what we have detected since we know if we have
 351          * a Beaglebone Black it supports 1GHz.
 352          */
 353         if (board_is_pb() || board_is_bone_lt())
 354                 freq = MPUPLL_M_1000;
 355
 356         switch (freq) {
 357         case MPUPLL_M_1000:
 358                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 359                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 360                 break;
 361         case MPUPLL_M_800:
 362                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 363                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 364                 break;
 365         case MPUPLL_M_720:
 366                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
 367                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 368                 break;
 369         case MPUPLL_M_600:
 370         case MPUPLL_M_500:
 371         case MPUPLL_M_300:
 372         default:
 373                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
 374                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 375                 break;
 376         }
 377
 378         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 379                                TPS65217_POWER_PATH,
 380                                usb_cur_lim,
 381                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 382                 puts("tps65217_reg_write failure\n");
 383
 384         /* Set DCDC3 (CORE) voltage to 1.10V */
 385         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 386                                     TPS65217_DCDC_VOLT_SEL_1100MV)) {
 387                 puts("tps65217_voltage_update failure\n");
 388                 return;
 389         }
 390
 391         /* Set DCDC2 (MPU) voltage */
 392         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 393                 puts("tps65217_voltage_update failure\n");
 394                 return;
 395         }
 396
 397         /*
 398          * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 399          * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 400          */
 401         if (board_is_bone()) {
 402                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 403                                        TPS65217_DEFLS1,
 404                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 405                                        TPS65217_LDO_MASK))
 406                         puts("tps65217_reg_write failure\n");
 407         } else {
 408                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 409                                        TPS65217_DEFLS1,
 410                                        TPS65217_LDO_VOLTAGE_OUT_1_8,
 411                                        TPS65217_LDO_MASK))
 412                         puts("tps65217_reg_write failure\n");
 413         }
 414
 415         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 416                                TPS65217_DEFLS2,
 417                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 418                                TPS65217_LDO_MASK))
 419                 puts("tps65217_reg_write failure\n");
 420 }
 421
 422 void scale_vcores_generic(int freq)
 423 {
 424         int sil_rev, mpu_vdd;
 425
 426         /*
 427          * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 428          * MPU frequencies we support we use a CORE voltage of
 429          * 1.10V.  For MPU voltage we need to switch based on
 430          * the frequency we are running at.
 431          */
 432         if (power_tps65910_init(0))
 433                 return;
 434         /*
 435          * Depending on MPU clock and PG we will need a different
 436          * VDD to drive at that speed.
 437          */
 438         sil_rev = readl(&cdev->deviceid) >> 28;
 439         mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 440
 441         /* Tell the TPS65910 to use i2c */
 442         tps65910_set_i2c_control();
 443
 444         /* First update MPU voltage. */
 445         if (tps65910_voltage_update(MPU, mpu_vdd))
 446                 return;
 447
 448         /* Second, update the CORE voltage. */
 449         if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
 450                 return;
 451
 452 }
 453
 454 void gpi2c_init(void)
 455 {
 456         /* When needed to be invoked prior to BSS initialization */
 457         static bool first_time = true;
 458
 459         if (first_time) {
 460                 enable_i2c0_pin_mux();
 461                 first_time = false;
 462         }
 463 }
 464
 465 void scale_vcores(void)
 466 {
 467         int freq;
 468
 469         gpi2c_init();
 470         freq = am335x_get_efuse_mpu_max_freq(cdev);
 471
 472         if (board_is_beaglebonex())
 473                 scale_vcores_bone(freq);
 474         else
 475                 scale_vcores_generic(freq);
 476 }
 477
 478 void set_uart_mux_conf(void)
 479 {
 480 #if CONFIG_CONS_INDEX == 1
 481         enable_uart0_pin_mux();
 482 #elif CONFIG_CONS_INDEX == 2
 483         enable_uart1_pin_mux();
 484 #elif CONFIG_CONS_INDEX == 3
 485         enable_uart2_pin_mux();
 486 #elif CONFIG_CONS_INDEX == 4
 487         enable_uart3_pin_mux();
 488 #elif CONFIG_CONS_INDEX == 5
 489         enable_uart4_pin_mux();
 490 #elif CONFIG_CONS_INDEX == 6
 491         enable_uart5_pin_mux();
 492 #endif
 493 }
 494
 495 void set_mux_conf_regs(void)
 496 {
 497         enable_board_pin_mux();
 498 }
 499
 500 const struct ctrl_ioregs ioregs_evmsk = {
 501         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 502         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 503         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 504         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 505         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 506 };
 507
 508 const struct ctrl_ioregs ioregs_bonelt = {
 509         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 510         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 511         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 512         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 513         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 514 };
 515
 516 const struct ctrl_ioregs ioregs_evm15 = {
 517         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 518         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 519         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 520         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 521         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 522 };
 523
 524 const struct ctrl_ioregs ioregs = {
 525         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 526         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 527         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 528         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 529         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 530 };
 531
 532 void sdram_init(void)
 533 {
 534         if (board_is_evm_sk()) {
 535                 /*
 536                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 537                  * This is safe enough to do on older revs.
 538                  */
 539                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 540                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 541         }
 542
 543         if (board_is_icev2()) {
 544                 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
 545                 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
 546         }
 547
 548         if (board_is_evm_sk())
 549                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 550                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 551         else if (board_is_pb() || board_is_bone_lt())
 552                 config_ddr(400, &ioregs_bonelt,
 553                            &ddr3_beagleblack_data,
 554                            &ddr3_beagleblack_cmd_ctrl_data,
 555                            &ddr3_beagleblack_emif_reg_data, 0);
 556         else if (board_is_evm_15_or_later())
 557                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 558                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 559         else if (board_is_icev2())
 560                 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 561                            &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 562                            0);
 563         else if (board_is_gp_evm())
 564                 config_ddr(266, &ioregs, &ddr2_data,
 565                            &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 566         else
 567                 config_ddr(266, &ioregs, &ddr2_data,
 568                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 569 }
 570 #endif
 571
 572 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 573         (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
 574 static void request_and_set_gpio(int gpio, char *name, int val)
 575 {
 576         int ret;
 577
 578         ret = gpio_request(gpio, name);
 579         if (ret < 0) {
 580                 printf("%s: Unable to request %s\n", __func__, name);
 581                 return;
 582         }
 583
 584         ret = gpio_direction_output(gpio, 0);
 585         if (ret < 0) {
 586                 printf("%s: Unable to set %s  as output\n", __func__, name);
 587                 goto err_free_gpio;
 588         }
 589
 590         gpio_set_value(gpio, val);
 591
 592         return;
 593
 594 err_free_gpio:
 595         gpio_free(gpio);
 596 }
 597
 598 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
 599 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
 600
 601 /**
 602  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
 603  * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
 604  * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
 605  * give 50MHz output for Eth0 and 1.
 606  */
 607 static struct clk_synth cdce913_data = {
 608         .id = 0x81,
 609         .capacitor = 0x90,
 610         .mux = 0x6d,
 611         .pdiv2 = 0x2,
 612         .pdiv3 = 0x2,
 613 };
 614 #endif
 615
 616 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
 617         defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
 618
 619 #define MAX_CPSW_SLAVES 2
 620
 621 /* At the moment, we do not want to stop booting for any failures here */
 622 int ft_board_setup(void *fdt, struct bd_info *bd)
 623 {
 624         const char *slave_path, *enet_name;
 625         int enetnode, slavenode, phynode;
 626         struct udevice *ethdev;
 627         char alias[16];
 628         u32 phy_id[2];
 629         int phy_addr;
 630         int i, ret;
 631
 632         /* phy address fixup needed only on beagle bone family */
 633         if (!board_is_beaglebonex())
 634                 goto done;
 635
 636         for (i = 0; i < MAX_CPSW_SLAVES; i++) {
 637                 sprintf(alias, "ethernet%d", i);
 638
 639                 slave_path = fdt_get_alias(fdt, alias);
 640                 if (!slave_path)
 641                         continue;
 642
 643                 slavenode = fdt_path_offset(fdt, slave_path);
 644                 if (slavenode < 0)
 645                         continue;
 646
 647                 enetnode = fdt_parent_offset(fdt, slavenode);
 648                 enet_name = fdt_get_name(fdt, enetnode, NULL);
 649
 650                 ethdev = eth_get_dev_by_name(enet_name);
 651                 if (!ethdev)
 652                         continue;
 653
 654                 phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
 655
 656                 /* check for phy_id as well as phy-handle properties */
 657                 ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
 658                                                  phy_id, 2);
 659                 if (ret == 2) {
 660                         if (phy_id[1] != phy_addr) {
 661                                 printf("fixing up phy_id for %s, old: %d, new: %d\n",
 662                                        alias, phy_id[1], phy_addr);
 663
 664                                 phy_id[0] = cpu_to_fdt32(phy_id[0]);
 665                                 phy_id[1] = cpu_to_fdt32(phy_addr);
 666                                 do_fixup_by_path(fdt, slave_path, "phy_id",
 667                                                  phy_id, sizeof(phy_id), 0);
 668                         }
 669                 } else {
 670                         phynode = fdtdec_lookup_phandle(fdt, slavenode,
 671                                                         "phy-handle");
 672                         if (phynode < 0)
 673                                 continue;
 674
 675                         ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
 676                         if (ret < 0)
 677                                 continue;
 678
 679                         if (ret != phy_addr) {
 680                                 printf("fixing up phy-handle for %s, old: %d, new: %d\n",
 681                                        alias, ret, phy_addr);
 682
 683                                 fdt_setprop_u32(fdt, phynode, "reg",
 684                                                 cpu_to_fdt32(phy_addr));
 685                         }
 686                 }
 687         }
 688
 689 done:
 690         return 0;
 691 }
 692 #endif
 693
 694 /*
 695  * Basic board specific setup.  Pinmux has been handled already.
 696  */
 697 int board_init(void)
 698 {
 699 #if defined(CONFIG_HW_WATCHDOG)
 700         hw_watchdog_init();
 701 #endif
 702
 703         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 704 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
 705         gpmc_init();
 706 #endif
 707
 708 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
 709         (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD)))
 710         if (board_is_icev2()) {
 711                 int rv;
 712                 u32 reg;
 713
 714                 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
 715                 /* Make J19 status available on GPIO1_26 */
 716                 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
 717
 718                 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
 719                 /*
 720                  * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
 721                  * jumpers near the port. Read the jumper value and set
 722                  * the pinmux, external mux and PHY clock accordingly.
 723                  * As jumper line is overridden by PHY RX_DV pin immediately
 724                  * after bootstrap (power-up/reset), we need to sample
 725                  * it during PHY reset using GPIO rising edge detection.
 726                  */
 727                 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
 728                 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
 729                 reg = readl(GPIO0_RISINGDETECT) | BIT(11);
 730                 writel(reg, GPIO0_RISINGDETECT);
 731                 reg = readl(GPIO1_RISINGDETECT) | BIT(26);
 732                 writel(reg, GPIO1_RISINGDETECT);
 733                 /* Reset PHYs to capture the Jumper setting */
 734                 gpio_set_value(GPIO_PHY_RESET, 0);
 735                 udelay(2);      /* PHY datasheet states 1uS min. */
 736                 gpio_set_value(GPIO_PHY_RESET, 1);
 737
 738                 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
 739                 if (reg) {
 740                         writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
 741                         /* RMII mode */
 742                         printf("ETH0, CPSW\n");
 743                 } else {
 744                         /* MII mode */
 745                         printf("ETH0, PRU\n");
 746                         cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
 747                 }
 748
 749                 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
 750                 if (reg) {
 751                         writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
 752                         /* RMII mode */
 753                         printf("ETH1, CPSW\n");
 754                         gpio_set_value(GPIO_MUX_MII_CTRL, 1);
 755                 } else {
 756                         /* MII mode */
 757                         printf("ETH1, PRU\n");
 758                         cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
 759                 }
 760
 761                 /* disable rising edge IRQs */
 762                 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
 763                 writel(reg, GPIO0_RISINGDETECT);
 764                 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
 765                 writel(reg, GPIO1_RISINGDETECT);
 766
 767                 rv = setup_clock_synthesizer(&cdce913_data);
 768                 if (rv) {
 769                         printf("Clock synthesizer setup failed %d\n", rv);
 770                         return rv;
 771                 }
 772
 773                 /* reset PHYs */
 774                 gpio_set_value(GPIO_PHY_RESET, 0);
 775                 udelay(2);      /* PHY datasheet states 1uS min. */
 776                 gpio_set_value(GPIO_PHY_RESET, 1);
 777         }
 778 #endif
 779
 780         return 0;
 781 }
 782
 783 #ifdef CONFIG_BOARD_LATE_INIT
 784 int board_late_init(void)
 785 {
 786         struct udevice *dev;
 787 #if !defined(CONFIG_SPL_BUILD)
 788         uint8_t mac_addr[6];
 789         uint32_t mac_hi, mac_lo;
 790 #endif
 791
 792 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 793         char *name = NULL;
 794
 795         if (board_is_bone_lt()) {
 796                 /* BeagleBoard.org BeagleBone Black Wireless: */
 797                 if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
 798                         name = "BBBW";
 799                 }
 800                 /* SeeedStudio BeagleBone Green Wireless */
 801                 if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
 802                         name = "BBGW";
 803                 }
 804                 /* BeagleBoard.org BeagleBone Blue */
 805                 if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
 806                         name = "BBBL";
 807                 }
 808         }
 809
 810         if (board_is_bbg1())
 811                 name = "BBG1";
 812         if (board_is_bben())
 813                 name = "BBEN";
 814         set_board_info_env(name);
 815
 816         /*
 817          * Default FIT boot on HS devices. Non FIT images are not allowed
 818          * on HS devices.
 819          */
 820         if (get_device_type() == HS_DEVICE)
 821                 env_set("boot_fit", "1");
 822 #endif
 823
 824 #if !defined(CONFIG_SPL_BUILD)
 825         /* try reading mac address from efuse */
 826         mac_lo = readl(&cdev->macid0l);
 827         mac_hi = readl(&cdev->macid0h);
 828         mac_addr[0] = mac_hi & 0xFF;
 829         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 830         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 831         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 832         mac_addr[4] = mac_lo & 0xFF;
 833         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 834
 835         if (!env_get("ethaddr")) {
 836                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 837
 838                 if (is_valid_ethaddr(mac_addr))
 839                         eth_env_set_enetaddr("ethaddr", mac_addr);
 840         }
 841
 842         mac_lo = readl(&cdev->macid1l);
 843         mac_hi = readl(&cdev->macid1h);
 844         mac_addr[0] = mac_hi & 0xFF;
 845         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 846         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 847         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 848         mac_addr[4] = mac_lo & 0xFF;
 849         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 850
 851         if (!env_get("eth1addr")) {
 852                 if (is_valid_ethaddr(mac_addr))
 853                         eth_env_set_enetaddr("eth1addr", mac_addr);
 854         }
 855 #endif
 856
 857         if (!env_get("serial#")) {
 858                 char *board_serial = env_get("board_serial");
 859                 char *ethaddr = env_get("ethaddr");
 860
 861                 if (!board_serial || !strncmp(board_serial, "unknown", 7))
 862                         env_set("serial#", ethaddr);
 863                 else
 864                         env_set("serial#", board_serial);
 865         }
 866
 867         /* Just probe the potentially supported cdce913 device */
 868         uclass_get_device_by_name(UCLASS_CLK, "cdce913@65", &dev);
 869
 870         return 0;
 871 }
 872 #endif
 873
 874 /* CPSW plat */
 875 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 876 struct cpsw_slave_data slave_data[] = {
 877         {
 878                 .slave_reg_ofs  = CPSW_SLAVE0_OFFSET,
 879                 .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
 880                 .phy_addr       = 0,
 881         },
 882         {
 883                 .slave_reg_ofs  = CPSW_SLAVE1_OFFSET,
 884                 .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
 885                 .phy_addr       = 1,
 886         },
 887 };
 888
 889 struct cpsw_platform_data am335_eth_data = {
 890         .cpsw_base              = CPSW_BASE,
 891         .version                = CPSW_CTRL_VERSION_2,
 892         .bd_ram_ofs             = CPSW_BD_OFFSET,
 893         .ale_reg_ofs            = CPSW_ALE_OFFSET,
 894         .cpdma_reg_ofs          = CPSW_CPDMA_OFFSET,
 895         .mdio_div               = CPSW_MDIO_DIV,
 896         .host_port_reg_ofs      = CPSW_HOST_PORT_OFFSET,
 897         .channels               = 8,
 898         .slaves                 = 2,
 899         .slave_data             = slave_data,
 900         .ale_entries            = 1024,
 901         .mac_control            = 0x20,
 902         .active_slave           = 0,
 903         .mdio_base              = 0x4a101000,
 904         .gmii_sel               = 0x44e10650,
 905         .phy_sel_compat         = "ti,am3352-cpsw-phy-sel",
 906         .syscon_addr            = 0x44e10630,
 907         .macid_sel_compat       = "cpsw,am33xx",
 908 };
 909
 910 struct eth_pdata cpsw_pdata = {
 911         .iobase = 0x4a100000,
 912         .phy_interface = 0,
 913         .priv_pdata = &am335_eth_data,
 914 };
 915
 916 U_BOOT_DRVINFO(am335x_eth) = {
 917         .name = "eth_cpsw",
 918         .plat = &cpsw_pdata,
 919 };
 920 #endif
 921
 922 #ifdef CONFIG_SPL_LOAD_FIT
 923 int board_fit_config_name_match(const char *name)
 924 {
 925         if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
 926                 return 0;
 927         else if (board_is_bone() && !strcmp(name, "am335x-bone"))
 928                 return 0;
 929         else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
 930                 return 0;
 931         else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
 932                 return 0;
 933         else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
 934                 return 0;
 935         else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
 936                 return 0;
 937         else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 938                 return 0;
 939         else if (board_is_bben() && !strcmp(name, "am335x-sancloud-bbe"))
 940                 return 0;
 941         else
 942                 return -1;
 943 }
 944 #endif
 945
 946 #ifdef CONFIG_TI_SECURE_DEVICE
 947 void board_fit_image_post_process(const void *fit, int node, void **p_image,
 948                                   size_t *p_size)
 949 {
 950         secure_boot_verify_image(p_image, p_size);
 951 }
 952 #endif
 953
 954 #if !CONFIG_IS_ENABLED(OF_CONTROL)
 955 static const struct omap_hsmmc_plat am335x_mmc0_plat = {
 956         .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
 957         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
 958         .cfg.f_min = 400000,
 959         .cfg.f_max = 52000000,
 960         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 961         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 962 };
 963
 964 U_BOOT_DRVINFO(am335x_mmc0) = {
 965         .name = "omap_hsmmc",
 966         .plat = &am335x_mmc0_plat,
 967 };
 968
 969 static const struct omap_hsmmc_plat am335x_mmc1_plat = {
 970         .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
 971         .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
 972         .cfg.f_min = 400000,
 973         .cfg.f_max = 52000000,
 974         .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
 975         .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
 976 };
 977
 978 U_BOOT_DRVINFO(am335x_mmc1) = {
 979         .name = "omap_hsmmc",
 980         .plat = &am335x_mmc1_plat,
 981 };
 982 #endif