board/tbs/tbs2910/tbs2910.c

   1 /*
   2  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <asm/arch/clock.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/iomux.h>
  10 #include <asm/arch/mx6-pins.h>
  11 #include <linux/errno.h>
  12 #include <asm/gpio.h>
  13 #include <asm/mach-imx/mxc_i2c.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/sata.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/video.h>
  18 #include <mmc.h>
  19 #include <fsl_esdhc.h>
  20 #include <miiphy.h>
  21 #include <netdev.h>
  22 #include <asm/arch/mxc_hdmi.h>
  23 #include <asm/arch/crm_regs.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <i2c.h>
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define WEAK_PULLUP     (PAD_CTL_PUS_47K_UP |                   \
  30         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  31         PAD_CTL_SRE_SLOW)
  32
  33 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  34         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  35         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  38         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  39         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  40
  41 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  42         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  43
  44 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  45         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  46         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  47
  48 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  49
  50 #ifdef CONFIG_SYS_I2C
  51 /* I2C1, SGTL5000 */
  52 static struct i2c_pads_info i2c_pad_info0 = {
  53         .scl = {
  54                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
  55                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
  56                 .gp = IMX_GPIO_NR(5, 27)
  57         },
  58         .sda = {
  59                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
  60                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
  61                 .gp = IMX_GPIO_NR(5, 26)
  62         }
  63 };
  64
  65 /* I2C2 HDMI */
  66 static struct i2c_pads_info i2c_pad_info1 = {
  67         .scl = {
  68                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  69                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  70                 .gp = IMX_GPIO_NR(4, 12)
  71         },
  72         .sda = {
  73                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  74                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  75                 .gp = IMX_GPIO_NR(4, 13)
  76         }
  77 };
  78
  79 /* I2C3, CON11, DS1307, PCIe_SMB */
  80 static struct i2c_pads_info i2c_pad_info2 = {
  81         .scl = {
  82                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
  83                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
  84                 .gp = IMX_GPIO_NR(1, 3)
  85         },
  86         .sda = {
  87                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
  88                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
  89                 .gp = IMX_GPIO_NR(1, 6)
  90         }
  91 };
  92 #endif /* CONFIG_SYS_I2C */
  93
  94 static iomux_v3_cfg_t const uart1_pads[] = {
  95         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  96         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  97 };
  98
  99 static iomux_v3_cfg_t const uart2_pads[] = {
 100         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 101         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 102 };
 103
 104 static iomux_v3_cfg_t const enet_pads[] = {
 105         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 106         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 107         MX6_PAD_RGMII_TXC__RGMII_TXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 108         MX6_PAD_RGMII_TD0__RGMII_TD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 109         MX6_PAD_RGMII_TD1__RGMII_TD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 110         MX6_PAD_RGMII_TD2__RGMII_TD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 111         MX6_PAD_RGMII_TD3__RGMII_TD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 113         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 114         MX6_PAD_RGMII_RXC__RGMII_RXC            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 115         MX6_PAD_RGMII_RD0__RGMII_RD0            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_RGMII_RD1__RGMII_RD1            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_RGMII_RD2__RGMII_RD2            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_RGMII_RD3__RGMII_RD3            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         /* AR8035 PHY Reset */
 121         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
 122 };
 123
 124 static iomux_v3_cfg_t const pcie_pads[] = {
 125         /* W_DISABLE# */
 126         MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
 127         /* PERST# */
 128         MX6_PAD_GPIO_17__GPIO7_IO12  | MUX_PAD_CTRL(NO_PAD_CTRL),
 129 };
 130
 131 int dram_init(void)
 132 {
 133         gd->ram_size = 2048ul * 1024 * 1024;
 134         return 0;
 135 }
 136
 137 static void setup_iomux_enet(void)
 138 {
 139         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 140
 141         /* Reset AR8035 PHY */
 142         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
 143         udelay(500);
 144         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
 145 }
 146
 147 static void setup_pcie(void)
 148 {
 149         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 150 }
 151
 152 static void setup_iomux_uart(void)
 153 {
 154         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 155         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 156 }
 157
 158 #ifdef CONFIG_FSL_ESDHC
 159 static iomux_v3_cfg_t const usdhc2_pads[] = {
 160         MX6_PAD_SD2_CLK__SD2_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 161         MX6_PAD_SD2_CMD__SD2_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 162         MX6_PAD_SD2_DAT0__SD2_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD2_DAT1__SD2_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD2_DAT2__SD2_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD2_DAT3__SD2_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 167 };
 168
 169 static iomux_v3_cfg_t const usdhc3_pads[] = {
 170         MX6_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171         MX6_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 172         MX6_PAD_SD3_DAT0__SD3_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 173         MX6_PAD_SD3_DAT1__SD3_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 174         MX6_PAD_SD3_DAT2__SD3_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 175         MX6_PAD_SD3_DAT3__SD3_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 176         MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 177 };
 178
 179 static iomux_v3_cfg_t const usdhc4_pads[] = {
 180         MX6_PAD_SD4_CLK__SD4_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 181         MX6_PAD_SD4_CMD__SD4_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 182         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 183         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 184         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 185         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 186         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 187         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 188         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 189         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 190 };
 191
 192 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 193         {USDHC2_BASE_ADDR},
 194         {USDHC3_BASE_ADDR},
 195         {USDHC4_BASE_ADDR},
 196 };
 197
 198 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 199 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 200
 201 int board_mmc_getcd(struct mmc *mmc)
 202 {
 203         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 204         int ret = 0;
 205
 206         switch (cfg->esdhc_base) {
 207         case USDHC2_BASE_ADDR:
 208                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 209                 break;
 210         case USDHC3_BASE_ADDR:
 211                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 212                 break;
 213         case USDHC4_BASE_ADDR:
 214                 ret = 1; /* eMMC/uSDHC4 is always present */
 215                 break;
 216         }
 217         return ret;
 218 }
 219
 220 int board_mmc_init(bd_t *bis)
 221 {
 222         /*
 223          * (U-Boot device node)    (Physical Port)
 224          * mmc0                    SD2
 225          * mmc1                    SD3
 226          * mmc2                    eMMC
 227          */
 228         int i, ret;
 229         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 230                 switch (i) {
 231                 case 0:
 232                         imx_iomux_v3_setup_multiple_pads(
 233                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 234                         gpio_direction_input(USDHC2_CD_GPIO);
 235                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 236                         break;
 237                 case 1:
 238                         imx_iomux_v3_setup_multiple_pads(
 239                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 240                         gpio_direction_input(USDHC3_CD_GPIO);
 241                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 242                         break;
 243                 case 2:
 244                         imx_iomux_v3_setup_multiple_pads(
 245                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 246                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 247                         break;
 248                 default:
 249                         printf("Warning: you configured more USDHC controllers"
 250                                "(%d) then supported by the board (%d)\n",
 251                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 252                         return -EINVAL;
 253                 }
 254                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 255                 if (ret)
 256                         return ret;
 257         }
 258         return 0;
 259 }
 260
 261 /* set environment device to boot device when booting from SD */
 262 int board_mmc_get_env_dev(int devno)
 263 {
 264         return devno - 1;
 265 }
 266
 267 int board_mmc_get_env_part(int devno)
 268 {
 269         return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
 270 }
 271 #endif /* CONFIG_FSL_ESDHC */
 272
 273 #ifdef CONFIG_VIDEO_IPUV3
 274 static void do_enable_hdmi(struct display_info_t const *dev)
 275 {
 276         imx_enable_hdmi_phy();
 277 }
 278
 279 struct display_info_t const displays[] = {{
 280         .bus    = -1,
 281         .addr   = 0,
 282         .pixfmt = IPU_PIX_FMT_RGB24,
 283         .detect = detect_hdmi,
 284         .enable = do_enable_hdmi,
 285         .mode   = {
 286                 .name           = "HDMI",
 287                 /* 1024x768@60Hz (VESA)*/
 288                 .refresh        = 60,
 289                 .xres           = 1024,
 290                 .yres           = 768,
 291                 .pixclock       = 15384,
 292                 .left_margin    = 160,
 293                 .right_margin   = 24,
 294                 .upper_margin   = 29,
 295                 .lower_margin   = 3,
 296                 .hsync_len      = 136,
 297                 .vsync_len      = 6,
 298                 .sync           = FB_SYNC_EXT,
 299                 .vmode          = FB_VMODE_NONINTERLACED
 300 } } };
 301 size_t display_count = ARRAY_SIZE(displays);
 302
 303 static void setup_display(void)
 304 {
 305         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 306         int reg;
 307         s32 timeout = 100000;
 308
 309         enable_ipu_clock();
 310         imx_setup_hdmi();
 311
 312         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 313         reg = readl(&ccm->analog_pll_video);
 314         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 315         writel(reg, &ccm->analog_pll_video);
 316
 317         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 318         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 319         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 320         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 321         writel(reg, &ccm->analog_pll_video);
 322
 323         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 324         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 325
 326         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 327         writel(reg, &ccm->analog_pll_video);
 328
 329         while (timeout--)
 330                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 331                         break;
 332         if (timeout < 0)
 333                 printf("Warning: video pll lock timeout!\n");
 334
 335         reg = readl(&ccm->analog_pll_video);
 336         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 337         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 338         writel(reg, &ccm->analog_pll_video);
 339
 340         /* gate ipu1_di0_clk */
 341         reg = readl(&ccm->CCGR3);
 342         reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
 343         writel(reg, &ccm->CCGR3);
 344
 345         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 346         reg = readl(&ccm->chsccdr);
 347         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 348                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 349                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 350         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 351                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 352                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 353         writel(reg, &ccm->chsccdr);
 354
 355         /* enable ipu1_di0_clk */
 356         reg = readl(&ccm->CCGR3);
 357         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 358         writel(reg, &ccm->CCGR3);
 359 }
 360 #endif /* CONFIG_VIDEO_IPUV3 */
 361
 362 static int ar8035_phy_fixup(struct phy_device *phydev)
 363 {
 364         unsigned short val;
 365
 366         /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
 367         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 368         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 369         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 370
 371         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 372         val &= 0xffe3;
 373         val |= 0x18;
 374         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 375
 376         /* introduce tx clock delay */
 377         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 378         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 379         val |= 0x0100;
 380         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 381
 382         return 0;
 383 }
 384
 385 int board_phy_config(struct phy_device *phydev)
 386 {
 387         ar8035_phy_fixup(phydev);
 388
 389         if (phydev->drv->config)
 390                 phydev->drv->config(phydev);
 391
 392         return 0;
 393 }
 394
 395 int board_eth_init(bd_t *bis)
 396 {
 397         setup_iomux_enet();
 398         setup_pcie();
 399         return cpu_eth_init(bis);
 400 }
 401
 402 int board_early_init_f(void)
 403 {
 404         setup_iomux_uart();
 405         return 0;
 406 }
 407
 408 #ifdef CONFIG_CMD_BMODE
 409 static const struct boot_mode board_boot_modes[] = {
 410         /* 4 bit bus width */
 411         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 412         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 413         /* 8 bit bus width */
 414         {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 415         {NULL,   0},
 416 };
 417 #endif
 418
 419 #ifdef CONFIG_USB_EHCI_MX6
 420 static iomux_v3_cfg_t const usb_otg_pads[] = {
 421         MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 422 };
 423 #endif
 424
 425 int board_init(void)
 426 {
 427         /* address of boot parameters */
 428         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 429
 430 #ifdef CONFIG_VIDEO_IPUV3
 431         setup_display();
 432 #endif
 433 #ifdef CONFIG_SYS_I2C
 434         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 435         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 436         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 437 #endif
 438 #ifdef CONFIG_DWC_AHSATA
 439         setup_sata();
 440 #endif
 441 #ifdef CONFIG_CMD_BMODE
 442         add_board_boot_modes(board_boot_modes);
 443 #endif
 444 #ifdef CONFIG_USB_EHCI_MX6
 445         imx_iomux_v3_setup_multiple_pads(
 446                 usb_otg_pads, ARRAY_SIZE(usb_otg_pads));
 447 #endif
 448         return 0;
 449 }
 450
 451 int checkboard(void)
 452 {
 453         puts("Board: TBS2910 Matrix ARM mini PC\n");
 454         return 0;
 455 }