board/somlabs/visionsom-6ull/visionsom-6ull.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017-2019 A. Karas, SomLabs
   4  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <init.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/crm_regs.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/global_data.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17 #include <asm/mach-imx/iomux-v3.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <asm/io.h>
  20 #include <common.h>
  21 #include <env.h>
  22 #include <fsl_esdhc_imx.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <linux/sizes.h>
  26 #include <mmc.h>
  27 #include <netdev.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  32         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  33         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  34
  35 int dram_init(void)
  36 {
  37         gd->ram_size = imx_ddr_size();
  38
  39         return 0;
  40 }
  41
  42 static iomux_v3_cfg_t const uart1_pads[] = {
  43         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  44         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  45 };
  46
  47 static void setup_iomux_uart(void)
  48 {
  49         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  50 }
  51
  52 #ifdef CONFIG_FEC_MXC
  53 static int setup_fec(void)
  54 {
  55         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  56         int ret;
  57
  58         /*
  59          * Use 50M anatop loopback REF_CLK1 for ENET1,
  60          * clear gpr1[13], set gpr1[17].
  61          */
  62         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  63                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  64
  65         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  66         if (ret)
  67                 return ret;
  68
  69         enable_enet_clk(1);
  70
  71         return 0;
  72 }
  73
  74 int board_phy_config(struct phy_device *phydev)
  75 {
  76         phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  77
  78         if (phydev->drv->config)
  79                 phydev->drv->config(phydev);
  80
  81         return 0;
  82 }
  83 #endif
  84
  85 int board_mmc_get_env_dev(int devno)
  86 {
  87         return devno;
  88 }
  89
  90 int mmc_map_to_kernel_blk(int devno)
  91 {
  92         return devno;
  93 }
  94
  95 int board_early_init_f(void)
  96 {
  97         setup_iomux_uart();
  98
  99         return 0;
 100 }
 101
 102 int board_init(void)
 103 {
 104         /* Address of boot parameters */
 105         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 106
 107 #ifdef CONFIG_SYS_I2C_LEGACY
 108         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 109 #endif
 110
 111 #ifdef CONFIG_FEC_MXC
 112         setup_fec();
 113 #endif
 114
 115         return 0;
 116 }
 117
 118 #ifdef CONFIG_CMD_BMODE
 119 static const struct boot_mode board_boot_modes[] = {
 120         /* 4 bit bus width */
 121         {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
 122         {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 123         {NULL,   0},
 124 };
 125 #endif
 126
 127 int board_late_init(void)
 128 {
 129 #ifdef CONFIG_CMD_BMODE
 130         add_board_boot_modes(board_boot_modes);
 131 #endif
 132
 133         if (is_cpu_type(MXC_CPU_MX6ULL))
 134                 env_set("board", "visionsom-6ull");
 135         else
 136                 env_set("board", "visionsom-6ul");
 137
 138         return 0;
 139 }
 140
 141 int checkboard(void)
 142 {
 143         printf("Board: SoMLabs VisionSOM-6UL%s\n",
 144                is_cpu_type(MXC_CPU_MX6ULL) ? "L" : "");
 145
 146         return 0;
 147 }