board/solidrun/mx6cuboxi/mx6cuboxi.c

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
   7  *
   8  * Based on SPL code from Solidrun tree, which is:
   9  * Author: Tungyi Lin <tungyilin1127@gmail.com>
  10  *
  11  * Derived from EDM_CF_IMX6 code by TechNexion,Inc
  12  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/iomux.h>
  20 #include <asm/arch/mx6-pins.h>
  21 #include <asm/arch/mxc_hdmi.h>
  22 #include <linux/errno.h>
  23 #include <asm/gpio.h>
  24 #include <asm/mach-imx/iomux-v3.h>
  25 #include <asm/mach-imx/sata.h>
  26 #include <asm/mach-imx/video.h>
  27 #include <mmc.h>
  28 #include <fsl_esdhc.h>
  29 #include <malloc.h>
  30 #include <miiphy.h>
  31 #include <netdev.h>
  32 #include <asm/arch/crm_regs.h>
  33 #include <asm/io.h>
  34 #include <asm/arch/sys_proto.h>
  35 #include <spl.h>
  36 #include <usb.h>
  37 #include <usb/ehci-ci.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  42         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  46         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  47         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  57
  58 #define ETH_PHY_RESET   IMX_GPIO_NR(4, 15)
  59 #define USB_H1_VBUS     IMX_GPIO_NR(1, 0)
  60
  61 int dram_init(void)
  62 {
  63         gd->ram_size = imx_ddr_size();
  64         return 0;
  65 }
  66
  67 static iomux_v3_cfg_t const uart1_pads[] = {
  68         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  69         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  70 };
  71
  72 static iomux_v3_cfg_t const usdhc2_pads[] = {
  73         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  75         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  76         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  79 };
  80
  81 static iomux_v3_cfg_t const hb_cbi_sense[] = {
  82         /* These pins are for sensing if it is a CuBox-i or a HummingBoard */
  83         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09  | MUX_PAD_CTRL(UART_PAD_CTRL)),
  84         IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04   | MUX_PAD_CTRL(UART_PAD_CTRL)),
  85 };
  86
  87 static iomux_v3_cfg_t const usb_pads[] = {
  88         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89 };
  90
  91 static void setup_iomux_uart(void)
  92 {
  93         SETUP_IOMUX_PADS(uart1_pads);
  94 }
  95
  96 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  97         {USDHC2_BASE_ADDR},
  98 };
  99
 100 int board_mmc_getcd(struct mmc *mmc)
 101 {
 102         return 1; /* uSDHC2 is always present */
 103 }
 104
 105 int board_mmc_init(bd_t *bis)
 106 {
 107         SETUP_IOMUX_PADS(usdhc2_pads);
 108         usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 109         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 110         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 111
 112         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 113 }
 114
 115 static iomux_v3_cfg_t const enet_pads[] = {
 116         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 117         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 118         /* AR8035 reset */
 119         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 120         /* AR8035 interrupt */
 121         IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 122         /* GPIO16 -> AR8035 25MHz */
 123         IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 124         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 125         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 126         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 127         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 128         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 129         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 130         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 131         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)),
 132         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 133         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 134         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 135         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 136         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 137         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 138         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 139         IOMUX_PADS(PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)),
 140 };
 141
 142 static void setup_iomux_enet(void)
 143 {
 144         SETUP_IOMUX_PADS(enet_pads);
 145
 146         gpio_direction_output(ETH_PHY_RESET, 0);
 147         mdelay(10);
 148         gpio_set_value(ETH_PHY_RESET, 1);
 149         udelay(100);
 150 }
 151
 152 int board_phy_config(struct phy_device *phydev)
 153 {
 154         if (phydev->drv->config)
 155                 phydev->drv->config(phydev);
 156
 157         return 0;
 158 }
 159
 160 /* On Cuboxi Ethernet PHY can be located at addresses 0x0 or 0x4 */
 161 #define ETH_PHY_MASK    ((1 << 0x0) | (1 << 0x4))
 162
 163 int board_eth_init(bd_t *bis)
 164 {
 165         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 166         struct mii_dev *bus;
 167         struct phy_device *phydev;
 168
 169         int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
 170         if (ret)
 171                 return ret;
 172
 173         /* set gpr1[ENET_CLK_SEL] */
 174         setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 175
 176         setup_iomux_enet();
 177
 178         bus = fec_get_miibus(IMX_FEC_BASE, -1);
 179         if (!bus)
 180                 return -EINVAL;
 181
 182         phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII);
 183         if (!phydev) {
 184                 ret = -EINVAL;
 185                 goto free_bus;
 186         }
 187
 188         debug("using phy at address %d\n", phydev->addr);
 189         ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
 190         if (ret)
 191                 goto free_phydev;
 192
 193         return 0;
 194
 195 free_phydev:
 196         free(phydev);
 197 free_bus:
 198         free(bus);
 199         return ret;
 200 }
 201
 202 #ifdef CONFIG_VIDEO_IPUV3
 203 static void do_enable_hdmi(struct display_info_t const *dev)
 204 {
 205         imx_enable_hdmi_phy();
 206 }
 207
 208 struct display_info_t const displays[] = {
 209         {
 210                 .bus    = -1,
 211                 .addr   = 0,
 212                 .pixfmt = IPU_PIX_FMT_RGB24,
 213                 .detect = detect_hdmi,
 214                 .enable = do_enable_hdmi,
 215                 .mode   = {
 216                         .name           = "HDMI",
 217                         /* 1024x768@60Hz (VESA)*/
 218                         .refresh        = 60,
 219                         .xres           = 1024,
 220                         .yres           = 768,
 221                         .pixclock       = 15384,
 222                         .left_margin    = 160,
 223                         .right_margin   = 24,
 224                         .upper_margin   = 29,
 225                         .lower_margin   = 3,
 226                         .hsync_len      = 136,
 227                         .vsync_len      = 6,
 228                         .sync           = FB_SYNC_EXT,
 229                         .vmode          = FB_VMODE_NONINTERLACED
 230                 }
 231         }
 232 };
 233
 234 size_t display_count = ARRAY_SIZE(displays);
 235
 236 static int setup_display(void)
 237 {
 238         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 239         int reg;
 240         int timeout = 100000;
 241
 242         enable_ipu_clock();
 243         imx_setup_hdmi();
 244
 245         /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
 246         setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
 247
 248         reg = readl(&ccm->analog_pll_video);
 249         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 250         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
 251         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 252         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
 253         writel(reg, &ccm->analog_pll_video);
 254
 255         writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
 256         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
 257
 258         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 259         writel(reg, &ccm->analog_pll_video);
 260
 261         while (timeout--)
 262                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 263                         break;
 264         if (timeout < 0) {
 265                 printf("Warning: video pll lock timeout!\n");
 266                 return -ETIMEDOUT;
 267         }
 268
 269         reg = readl(&ccm->analog_pll_video);
 270         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 271         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 272         writel(reg, &ccm->analog_pll_video);
 273
 274         /* gate ipu1_di0_clk */
 275         clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 276
 277         /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
 278         reg = readl(&ccm->chsccdr);
 279         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
 280                  MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
 281                  MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 282         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
 283                (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
 284                (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 285         writel(reg, &ccm->chsccdr);
 286
 287         /* enable ipu1_di0_clk */
 288         setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 289
 290         return 0;
 291 }
 292 #endif /* CONFIG_VIDEO_IPUV3 */
 293
 294 #ifdef CONFIG_USB_EHCI_MX6
 295 static void setup_usb(void)
 296 {
 297         SETUP_IOMUX_PADS(usb_pads);
 298 }
 299
 300 int board_ehci_hcd_init(int port)
 301 {
 302         if (port == 1)
 303                 gpio_direction_output(USB_H1_VBUS, 1);
 304
 305         return 0;
 306 }
 307 #endif
 308
 309 int board_early_init_f(void)
 310 {
 311         setup_iomux_uart();
 312
 313 #ifdef CONFIG_CMD_SATA
 314         setup_sata();
 315 #endif
 316
 317 #ifdef CONFIG_USB_EHCI_MX6
 318         setup_usb();
 319 #endif
 320         return 0;
 321 }
 322
 323 int board_init(void)
 324 {
 325         int ret = 0;
 326
 327         /* address of boot parameters */
 328         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 329
 330 #ifdef CONFIG_VIDEO_IPUV3
 331         ret = setup_display();
 332 #endif
 333
 334         return ret;
 335 }
 336
 337 static bool is_hummingboard(void)
 338 {
 339         int val1, val2;
 340
 341         SETUP_IOMUX_PADS(hb_cbi_sense);
 342
 343         gpio_direction_input(IMX_GPIO_NR(4, 9));
 344         gpio_direction_input(IMX_GPIO_NR(3, 4));
 345
 346         val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
 347         val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
 348
 349         /*
 350          * Machine selection -
 351          * Machine        val1, val2
 352          * -------------------------
 353          * HB2            x     x
 354          * HB rev 3.x     x     0
 355          * CBi            0     1
 356          * HB             1     1
 357          */
 358
 359         if (val2 == 0)
 360                 return true;
 361         else if (val1 == 0)
 362                 return false;
 363         else
 364                 return true;
 365 }
 366
 367 static bool is_hummingboard2(void)
 368 {
 369         int val1;
 370
 371         SETUP_IOMUX_PADS(hb_cbi_sense);
 372
 373         gpio_direction_input(IMX_GPIO_NR(2, 8));
 374
 375         val1 = gpio_get_value(IMX_GPIO_NR(2, 8));
 376
 377         /*
 378          * Machine selection -
 379          * Machine        val1
 380          * -------------------
 381          * HB2            0
 382          * HB rev 3.x     x
 383          * CBi            x
 384          * HB             x
 385          */
 386
 387         if (val1 == 0)
 388                 return true;
 389         else
 390                 return false;
 391 }
 392
 393 int checkboard(void)
 394 {
 395         if (is_hummingboard2())
 396                 puts("Board: MX6 Hummingboard2\n");
 397         else if (is_hummingboard())
 398                 puts("Board: MX6 Hummingboard\n");
 399         else
 400                 puts("Board: MX6 Cubox-i\n");
 401
 402         return 0;
 403 }
 404
 405 int board_late_init(void)
 406 {
 407 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 408         if (is_hummingboard2())
 409                 env_set("board_name", "HUMMINGBOARD2");
 410         else if (is_hummingboard())
 411                 env_set("board_name", "HUMMINGBOARD");
 412         else
 413                 env_set("board_name", "CUBOXI");
 414
 415         if (is_mx6dq())
 416                 env_set("board_rev", "MX6Q");
 417         else
 418                 env_set("board_rev", "MX6DL");
 419 #endif
 420
 421         return 0;
 422 }
 423
 424 #ifdef CONFIG_SPL_BUILD
 425 #include <asm/arch/mx6-ddr.h>
 426 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
 427         .dram_sdclk_0 =  0x00020030,
 428         .dram_sdclk_1 =  0x00020030,
 429         .dram_cas =  0x00020030,
 430         .dram_ras =  0x00020030,
 431         .dram_reset =  0x000c0030,
 432         .dram_sdcke0 =  0x00003000,
 433         .dram_sdcke1 =  0x00003000,
 434         .dram_sdba2 =  0x00000000,
 435         .dram_sdodt0 =  0x00003030,
 436         .dram_sdodt1 =  0x00003030,
 437         .dram_sdqs0 =  0x00000030,
 438         .dram_sdqs1 =  0x00000030,
 439         .dram_sdqs2 =  0x00000030,
 440         .dram_sdqs3 =  0x00000030,
 441         .dram_sdqs4 =  0x00000030,
 442         .dram_sdqs5 =  0x00000030,
 443         .dram_sdqs6 =  0x00000030,
 444         .dram_sdqs7 =  0x00000030,
 445         .dram_dqm0 =  0x00020030,
 446         .dram_dqm1 =  0x00020030,
 447         .dram_dqm2 =  0x00020030,
 448         .dram_dqm3 =  0x00020030,
 449         .dram_dqm4 =  0x00020030,
 450         .dram_dqm5 =  0x00020030,
 451         .dram_dqm6 =  0x00020030,
 452         .dram_dqm7 =  0x00020030,
 453 };
 454
 455 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
 456         .dram_sdclk_0 = 0x00000028,
 457         .dram_sdclk_1 = 0x00000028,
 458         .dram_cas =     0x00000028,
 459         .dram_ras =     0x00000028,
 460         .dram_reset =   0x000c0028,
 461         .dram_sdcke0 =  0x00003000,
 462         .dram_sdcke1 =  0x00003000,
 463         .dram_sdba2 =   0x00000000,
 464         .dram_sdodt0 =  0x00003030,
 465         .dram_sdodt1 =  0x00003030,
 466         .dram_sdqs0 =   0x00000028,
 467         .dram_sdqs1 =   0x00000028,
 468         .dram_sdqs2 =   0x00000028,
 469         .dram_sdqs3 =   0x00000028,
 470         .dram_sdqs4 =   0x00000028,
 471         .dram_sdqs5 =   0x00000028,
 472         .dram_sdqs6 =   0x00000028,
 473         .dram_sdqs7 =   0x00000028,
 474         .dram_dqm0 =    0x00000028,
 475         .dram_dqm1 =    0x00000028,
 476         .dram_dqm2 =    0x00000028,
 477         .dram_dqm3 =    0x00000028,
 478         .dram_dqm4 =    0x00000028,
 479         .dram_dqm5 =    0x00000028,
 480         .dram_dqm6 =    0x00000028,
 481         .dram_dqm7 =    0x00000028,
 482 };
 483
 484 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
 485         .grp_ddr_type =  0x000C0000,
 486         .grp_ddrmode_ctl =  0x00020000,
 487         .grp_ddrpke =  0x00000000,
 488         .grp_addds =  0x00000030,
 489         .grp_ctlds =  0x00000030,
 490         .grp_ddrmode =  0x00020000,
 491         .grp_b0ds =  0x00000030,
 492         .grp_b1ds =  0x00000030,
 493         .grp_b2ds =  0x00000030,
 494         .grp_b3ds =  0x00000030,
 495         .grp_b4ds =  0x00000030,
 496         .grp_b5ds =  0x00000030,
 497         .grp_b6ds =  0x00000030,
 498         .grp_b7ds =  0x00000030,
 499 };
 500
 501 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 502         .grp_ddr_type = 0x000c0000,
 503         .grp_ddrmode_ctl = 0x00020000,
 504         .grp_ddrpke = 0x00000000,
 505         .grp_addds = 0x00000028,
 506         .grp_ctlds = 0x00000028,
 507         .grp_ddrmode = 0x00020000,
 508         .grp_b0ds = 0x00000028,
 509         .grp_b1ds = 0x00000028,
 510         .grp_b2ds = 0x00000028,
 511         .grp_b3ds = 0x00000028,
 512         .grp_b4ds = 0x00000028,
 513         .grp_b5ds = 0x00000028,
 514         .grp_b6ds = 0x00000028,
 515         .grp_b7ds = 0x00000028,
 516 };
 517
 518 /* microSOM with Dual processor and 1GB memory */
 519 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = {
 520         .p0_mpwldectrl0 =  0x00000000,
 521         .p0_mpwldectrl1 =  0x00000000,
 522         .p1_mpwldectrl0 =  0x00000000,
 523         .p1_mpwldectrl1 =  0x00000000,
 524         .p0_mpdgctrl0 =    0x0314031c,
 525         .p0_mpdgctrl1 =    0x023e0304,
 526         .p1_mpdgctrl0 =    0x03240330,
 527         .p1_mpdgctrl1 =    0x03180260,
 528         .p0_mprddlctl =    0x3630323c,
 529         .p1_mprddlctl =    0x3436283a,
 530         .p0_mpwrdlctl =    0x36344038,
 531         .p1_mpwrdlctl =    0x422a423c,
 532 };
 533
 534 /* microSOM with Quad processor and 2GB memory */
 535 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
 536         .p0_mpwldectrl0 =  0x00000000,
 537         .p0_mpwldectrl1 =  0x00000000,
 538         .p1_mpwldectrl0 =  0x00000000,
 539         .p1_mpwldectrl1 =  0x00000000,
 540         .p0_mpdgctrl0 =    0x0314031c,
 541         .p0_mpdgctrl1 =    0x023e0304,
 542         .p1_mpdgctrl0 =    0x03240330,
 543         .p1_mpdgctrl1 =    0x03180260,
 544         .p0_mprddlctl =    0x3630323c,
 545         .p1_mprddlctl =    0x3436283a,
 546         .p0_mpwrdlctl =    0x36344038,
 547         .p1_mpwrdlctl =    0x422a423c,
 548 };
 549
 550 /* microSOM with Solo processor and 512MB memory */
 551 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = {
 552         .p0_mpwldectrl0 = 0x0045004D,
 553         .p0_mpwldectrl1 = 0x003A0047,
 554         .p0_mpdgctrl0 =   0x023C0224,
 555         .p0_mpdgctrl1 =   0x02000220,
 556         .p0_mprddlctl =   0x44444846,
 557         .p0_mpwrdlctl =   0x32343032,
 558 };
 559
 560 /* microSOM with Dual lite processor and 1GB memory */
 561 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = {
 562         .p0_mpwldectrl0 =  0x0045004D,
 563         .p0_mpwldectrl1 =  0x003A0047,
 564         .p1_mpwldectrl0 =  0x001F001F,
 565         .p1_mpwldectrl1 =  0x00210035,
 566         .p0_mpdgctrl0 =    0x023C0224,
 567         .p0_mpdgctrl1 =    0x02000220,
 568         .p1_mpdgctrl0 =    0x02200220,
 569         .p1_mpdgctrl1 =    0x02040208,
 570         .p0_mprddlctl =    0x44444846,
 571         .p1_mprddlctl =    0x4042463C,
 572         .p0_mpwrdlctl =    0x32343032,
 573         .p1_mpwrdlctl =    0x36363430,
 574 };
 575
 576 static struct mx6_ddr3_cfg mem_ddr_2g = {
 577         .mem_speed = 1600,
 578         .density   = 2,
 579         .width     = 16,
 580         .banks     = 8,
 581         .rowaddr   = 14,
 582         .coladdr   = 10,
 583         .pagesz    = 2,
 584         .trcd      = 1375,
 585         .trcmin    = 4875,
 586         .trasmin   = 3500,
 587 };
 588
 589 static struct mx6_ddr3_cfg mem_ddr_4g = {
 590         .mem_speed = 1600,
 591         .density = 4,
 592         .width = 16,
 593         .banks = 8,
 594         .rowaddr = 15,
 595         .coladdr = 10,
 596         .pagesz = 2,
 597         .trcd = 1375,
 598         .trcmin = 4875,
 599         .trasmin = 3500,
 600 };
 601
 602 static void ccgr_init(void)
 603 {
 604         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 605
 606         writel(0x00C03F3F, &ccm->CCGR0);
 607         writel(0x0030FC03, &ccm->CCGR1);
 608         writel(0x0FFFC000, &ccm->CCGR2);
 609         writel(0x3FF00000, &ccm->CCGR3);
 610         writel(0x00FFF300, &ccm->CCGR4);
 611         writel(0x0F0000C3, &ccm->CCGR5);
 612         writel(0x000003FF, &ccm->CCGR6);
 613 }
 614
 615 static void spl_dram_init(int width)
 616 {
 617         struct mx6_ddr_sysinfo sysinfo = {
 618                 /* width of data bus: 0=16, 1=32, 2=64 */
 619                 .dsize = width / 32,
 620                 /* config for full 4GB range so that get_mem_size() works */
 621                 .cs_density = 32,       /* 32Gb per CS */
 622                 .ncs = 1,               /* single chip select */
 623                 .cs1_mirror = 0,
 624                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 625                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 626                 .walat = 1,     /* Write additional latency */
 627                 .ralat = 5,     /* Read additional latency */
 628                 .mif3_mode = 3, /* Command prediction working mode */
 629                 .bi_on = 1,     /* Bank interleaving enabled */
 630                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 631                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 632                 .ddr_type = DDR_TYPE_DDR3,
 633                 .refsel = 1,    /* Refresh cycles at 32KHz */
 634                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 635         };
 636
 637         if (is_mx6dq())
 638                 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
 639         else
 640                 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
 641
 642         if (is_cpu_type(MXC_CPU_MX6D))
 643                 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g);
 644         else if (is_cpu_type(MXC_CPU_MX6Q))
 645                 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
 646         else if (is_cpu_type(MXC_CPU_MX6DL))
 647                 mx6_dram_cfg(&sysinfo, &mx6dl_1g_mmcd_calib, &mem_ddr_2g);
 648         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 649                 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g);
 650 }
 651
 652 void board_init_f(ulong dummy)
 653 {
 654         /* setup AIPS and disable watchdog */
 655         arch_cpu_init();
 656
 657         ccgr_init();
 658         gpr_init();
 659
 660         /* iomux and setup of i2c */
 661         board_early_init_f();
 662
 663         /* setup GP timer */
 664         timer_init();
 665
 666         /* UART clocks enabled and gd valid - init serial console */
 667         preloader_console_init();
 668
 669         /* DDR initialization */
 670         if (is_cpu_type(MXC_CPU_MX6SOLO))
 671                 spl_dram_init(32);
 672         else
 673                 spl_dram_init(64);
 674
 675         /* Clear the BSS. */
 676         memset(__bss_start, 0, __bss_end - __bss_start);
 677
 678         /* load/boot image from boot device */
 679         board_init_r(NULL, 0);
 680 }
 681 #endif