board/sandburst/karef/karef.c

   1 /*
   2  *  Copyright (C) 2005 Sandburst Corporation
   3  *  Travis B. Sawyer
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <config.h>
  25 #include <common.h>
  26 #include <command.h>
  27 #include "karef.h"
  28 #include "karef_version.h"
  29 #include <timestamp.h>
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32 #include <spd_sdram.h>
  33 #include <i2c.h>
  34 #include "../common/sb_common.h"
  35 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
  36     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
  37 #include <net.h>
  38 #endif
  39
  40 void fpga_init (void);
  41
  42 KAREF_BOARD_ID_ST board_id_as[] =
  43 {
  44         {"Undefined"},                       /* Not specified */
  45         {"Kamino Reference Design"},
  46         {"Reserved"},                        /* Reserved for future use */
  47         {"Reserved"},                        /* Reserved for future use */
  48 };
  49
  50 KAREF_BOARD_ID_ST ofem_board_id_as[] =
  51 {
  52         {"Undefined"},
  53         {"1x10 + 10x2"},
  54         {"Reserved"},
  55         {"Reserved"},
  56 };
  57
  58 /*************************************************************************
  59  *  board_early_init_f
  60  *
  61  *  Setup chip selects, initialize the Opto-FPGA, initialize
  62  *  interrupt polarity and triggers.
  63  ************************************************************************/
  64 int board_early_init_f (void)
  65 {
  66         ppc440_gpio_regs_t *gpio_regs;
  67
  68         /* Enable GPIO interrupts */
  69         mtsdr(SDR0_PFC0, 0x00103E00);
  70
  71         /* Setup access for LEDs, and system topology info */
  72         gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
  73         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  74         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  75
  76         /* Turn on all the leds for now */
  77         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  78
  79         /*--------------------------------------------------------------------+
  80           | Initialize EBC CONFIG
  81           +-------------------------------------------------------------------*/
  82         mtebc(EBC0_CFG,
  83               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  84               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  85               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  86               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  87               EBC_CFG_PR_32);
  88
  89         /*--------------------------------------------------------------------+
  90           | 1/2 MB FLASH. Initialize bank 0 with default values.
  91           +-------------------------------------------------------------------*/
  92         mtebc(PB0AP,
  93               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  94               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  95               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  96               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  97               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  98               EBC_BXAP_PEN_DISABLED);
  99
 100         mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
 101               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 102         /*--------------------------------------------------------------------+
 103           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
 104           +-------------------------------------------------------------------*/
 105         mtebc(PB1AP,
 106               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
 107               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 108               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 109               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
 110               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 111               EBC_BXAP_PEN_DISABLED);
 112
 113         mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
 114               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 115
 116         /*--------------------------------------------------------------------+
 117           | Compact Flash, uses 2 Chip Selects (2 & 6)
 118           +-------------------------------------------------------------------*/
 119         mtebc(PB2AP,
 120               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 121               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 122               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 123               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 124               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 125               EBC_BXAP_PEN_DISABLED);
 126
 127         mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 128               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 129
 130         /*--------------------------------------------------------------------+
 131           | KaRef Scan FPGA. Initialize bank 3 with default values.
 132           +-------------------------------------------------------------------*/
 133         mtebc(PB5AP,
 134               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 135               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 136               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 137               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 138               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 139
 140         mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
 141               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 142
 143         /*--------------------------------------------------------------------+
 144           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 145           | Initialize bank 4 with default values.
 146           +-------------------------------------------------------------------*/
 147         mtebc(PB4AP,
 148               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 149               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 150               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 151               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 152               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 153
 154         mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
 155               EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 156
 157         /*--------------------------------------------------------------------+
 158           | OFEM FPGA  Initialize bank 5 with default values.
 159           +-------------------------------------------------------------------*/
 160         mtebc(PB3AP,
 161               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 162               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 163               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 164               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 165               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 166
 167
 168         mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) |
 169               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 170
 171
 172         /*--------------------------------------------------------------------+
 173           | Compact Flash, uses 2 Chip Selects (2 & 6)
 174           +-------------------------------------------------------------------*/
 175         mtebc(PB6AP,
 176               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 177               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 178               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 179               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 180               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 181               EBC_BXAP_PEN_DISABLED);
 182
 183         mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 184               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 185
 186         /*--------------------------------------------------------------------+
 187           | BME-32. Initialize bank 7 with default values.
 188           +-------------------------------------------------------------------*/
 189         mtebc(PB7AP,
 190               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 191               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 192               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 193               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 194               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 195
 196         mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
 197               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 198
 199         /*--------------------------------------------------------------------+
 200          * Setup the interrupt controller polarities, triggers, etc.
 201          +-------------------------------------------------------------------*/
 202         /*
 203          * Because of the interrupt handling rework to handle 440GX interrupts
 204          * with the common code, we needed to change names of the UIC registers.
 205          * Here the new relationship:
 206          *
 207          * U-Boot name  440GX name
 208          * -----------------------
 209          * UIC0         UICB0
 210          * UIC1         UIC0
 211          * UIC2         UIC1
 212          * UIC3         UIC2
 213          */
 214         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 215         mtdcr (UIC1ER, 0x00000000);     /* disable all */
 216         mtdcr (UIC1CR, 0x00000000);     /* all non- critical */
 217         mtdcr (UIC1PR, 0xfffffe03);     /* polarity */
 218         mtdcr (UIC1TR, 0x01c00000);     /* trigger edge vs level */
 219         mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
 220         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 221
 222         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 223         mtdcr (UIC2ER, 0x00000000);     /* disable all */
 224         mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
 225         mtdcr (UIC2PR, 0xffffc8ff);     /* polarity */
 226         mtdcr (UIC2TR, 0x00ff0000);     /* trigger edge vs level */
 227         mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
 228         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 229
 230         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 231         mtdcr (UIC3ER, 0x00000000);     /* disable all */
 232         mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
 233         mtdcr (UIC3PR, 0xffff83ff);     /* polarity */
 234         mtdcr (UIC3TR, 0x00ff8c0f);     /* trigger edge vs level */
 235         mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
 236         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 237
 238         mtdcr (UIC0SR, 0xfc000000);     /* clear all */
 239         mtdcr (UIC0ER, 0x00000000);     /* disable all */
 240         mtdcr (UIC0CR, 0x00000000);     /* all non-critical */
 241         mtdcr (UIC0PR, 0xfc000000);
 242         mtdcr (UIC0TR, 0x00000000);
 243         mtdcr (UIC0VR, 0x00000001);
 244
 245         fpga_init();
 246
 247         return 0;
 248 }
 249
 250
 251 /*************************************************************************
 252  *  checkboard
 253  *
 254  *  Dump pertinent info to the console
 255  ************************************************************************/
 256 int checkboard (void)
 257 {
 258         sys_info_t sysinfo;
 259         unsigned char brd_rev, brd_id;
 260         unsigned short sernum;
 261         unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
 262         unsigned char ofem_brd_rev, ofem_brd_id;
 263         KAREF_FPGA_REGS_ST *karef_ps;
 264         OFEM_FPGA_REGS_ST *ofem_ps;
 265
 266         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 267         ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 268
 269         scan_id = (unsigned char)((karef_ps->revision_ul &
 270                                    SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
 271                                   >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
 272
 273         scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
 274                                    >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
 275
 276         brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
 277                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
 278
 279         brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
 280                                  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
 281
 282         ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 283                                       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 284
 285         ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
 286                                        >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
 287
 288         if (0xF != ofem_brd_id) {
 289                 ofem_id = (unsigned char)((ofem_ps->revision_ul &
 290                                            SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
 291                                           >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
 292
 293                 ofem_rev = (unsigned char)((ofem_ps->revision_ul &
 294                                             SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
 295                                            >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
 296         }
 297
 298         get_sys_info (&sysinfo);
 299
 300         sernum = sbcommon_get_serial_number();
 301
 302         printf ("Board: Sandburst Corporation Kamino Reference Design "
 303                 "Serial Number: %d\n", sernum);
 304         printf ("%s\n", KAREF_U_BOOT_REL_STR);
 305
 306         printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 307         if (sbcommon_get_master()) {
 308                 printf("Slot 0 - Master\nSlave board");
 309                 if (sbcommon_secondary_present())
 310                         printf(" present\n");
 311                 else
 312                         printf(" not detected\n");
 313         } else {
 314                 printf("Slot 1 - Slave\n\n");
 315         }
 316
 317         printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
 318         printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
 319         if(0xF != ofem_brd_id) {
 320                 printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
 321                 printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
 322         }
 323
 324         /* Fix the ack in the bme 32 */
 325         udelay(5000);
 326         out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 327         asm("eieio");
 328
 329
 330         return (0);
 331 }
 332
 333 /*************************************************************************
 334  *  misc_init_f
 335  *
 336  *  Initialize I2C bus one to gain access to the fans
 337  ************************************************************************/
 338 int misc_init_f (void)
 339 {
 340         /* Turn on i2c bus 1 */
 341         puts ("I2C1:  ");
 342         i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 343         puts ("ready\n");
 344
 345         /* Turn on fans 3 & 4 */
 346         sbcommon_fans();
 347
 348         return (0);
 349 }
 350
 351 /*************************************************************************
 352  *  misc_init_r
 353  *
 354  *  Do nothing.
 355  ************************************************************************/
 356 int misc_init_r (void)
 357 {
 358         unsigned short sernum;
 359         char envstr[255];
 360         uchar enetaddr[6];
 361         KAREF_FPGA_REGS_ST *karef_ps;
 362         OFEM_FPGA_REGS_ST *ofem_ps;
 363
 364         if(NULL != getenv("secondserial")) {
 365                 puts("secondserial is set, switching to second serial port\n");
 366                 setenv("stderr", "serial1");
 367                 setenv("stdout", "serial1");
 368                 setenv("stdin", "serial1");
 369         }
 370
 371         setenv("ubrelver", KAREF_U_BOOT_REL_STR);
 372
 373         memset(envstr, 0, 255);
 374         sprintf (envstr, "Built %s %s by %s",
 375                  U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 376         setenv("bldstr", envstr);
 377         saveenv();
 378
 379         if( getenv("autorecover")) {
 380                 setenv("autorecover", NULL);
 381                 saveenv();
 382                 sernum = sbcommon_get_serial_number();
 383
 384                 printf("\nSetting up environment for automatic filesystem recovery\n");
 385                 /*
 386                  * Setup default bootargs
 387                  */
 388                 memset(envstr, 0, 255);
 389
 390                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 391                         "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 392                         sernum, sernum);
 393                 setenv("bootargs", envstr);
 394
 395                 /*
 396                  * Setup Default boot command
 397                  */
 398                 setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 399                        "fatload ide 0 8100000 pramdisk;"
 400                        "bootm 8000000 8100000");
 401
 402                 printf("Done.  Please type allow the system to continue to boot\n");
 403         }
 404
 405         if( getenv("fakeled")) {
 406                 karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 407                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 408                 ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
 409                 karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
 410                 setenv("bootdelay", "-1");
 411                 saveenv();
 412                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 413         }
 414
 415 #ifdef CONFIG_HAS_ETH0
 416         if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 417                 board_get_enetaddr(0, enetaddr);
 418                 eth_setenv_enetaddr("ethaddr", enetaddr);
 419         }
 420 #endif
 421
 422 #ifdef CONFIG_HAS_ETH1
 423         if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
 424                 board_get_enetaddr(1, enetaddr);
 425                 eth_setenv_enetaddr("eth1addr", enetaddr);
 426         }
 427 #endif
 428
 429 #ifdef CONFIG_HAS_ETH2
 430         if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
 431                 board_get_enetaddr(2, enetaddr);
 432                 eth_setenv_enetaddr("eth2addr", enetaddr);
 433         }
 434 #endif
 435
 436 #ifdef CONFIG_HAS_ETH3
 437         if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
 438                 board_get_enetaddr(3, enetaddr);
 439                 eth_setenv_enetaddr("eth3addr", enetaddr);
 440         }
 441 #endif
 442
 443         return (0);
 444 }
 445
 446 /*************************************************************************
 447  *  ide_set_reset
 448  ************************************************************************/
 449 #ifdef CONFIG_IDE_RESET
 450 void ide_set_reset(int on)
 451 {
 452         KAREF_FPGA_REGS_ST *karef_ps;
 453         /* TODO: ide reset */
 454         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 455
 456         if (on) {
 457                 karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 458         } else {
 459                 karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
 460         }
 461 }
 462 #endif /* CONFIG_IDE_RESET */
 463
 464 /*************************************************************************
 465  *  fpga_init
 466  ************************************************************************/
 467 void fpga_init(void)
 468 {
 469         KAREF_FPGA_REGS_ST *karef_ps;
 470         OFEM_FPGA_REGS_ST *ofem_ps;
 471         unsigned char ofem_id;
 472         unsigned long tmp;
 473
 474         /* Ensure we have power all around */
 475         udelay(500);
 476
 477         karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 478         tmp =
 479                 SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
 480                 SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
 481                 SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
 482                 SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
 483                 SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
 484                 SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
 485                 SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
 486                 SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
 487                 SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
 488
 489         karef_ps->reset_ul = tmp;
 490
 491         /*
 492          * Wait a bit to allow the ofem fpga to get its brains
 493          */
 494         udelay(5000);
 495
 496         /*
 497          * Check to see if the ofem is there
 498          */
 499         ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
 500                                   >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
 501         if(0xF != ofem_id) {
 502                 tmp =
 503                         SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
 504                         SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
 505                         SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
 506
 507                 ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 508                 ofem_ps->reset_ul = tmp;
 509
 510                 ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
 511         }
 512
 513         karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
 514
 515         asm("eieio");
 516
 517         return;
 518 }
 519
 520 int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 521 {
 522         unsigned short sernum;
 523         char envstr[255];
 524
 525         sernum = sbcommon_get_serial_number();
 526
 527         memset(envstr, 0, 255);
 528         /*
 529          * Setup our ip address
 530          */
 531         sprintf(envstr, "10.100.70.%d", sernum);
 532
 533         setenv("ipaddr", envstr);
 534         /*
 535          * Setup the host ip address
 536          */
 537         setenv("serverip", "10.100.17.10");
 538
 539         /*
 540          * Setup default bootargs
 541          */
 542         memset(envstr, 0, 255);
 543
 544         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 545                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
 546                 "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
 547                 "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
 548                 sernum, sernum, sernum);
 549
 550         setenv("bootargs_nfs", envstr);
 551         setenv("bootargs", envstr);
 552
 553         /*
 554          * Setup CF bootargs
 555          */
 556         memset(envstr, 0, 255);
 557
 558         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 559                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
 560                 sernum, sernum);
 561
 562         setenv("bootargs_cf", envstr);
 563
 564         /*
 565          * Setup Default boot command
 566          */
 567         setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
 568         setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
 569
 570         /*
 571          * Setup compact flash boot command
 572          */
 573         setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
 574
 575         saveenv();
 576
 577         return(1);
 578 }
 579
 580 int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 581 {
 582         unsigned short sernum;
 583         char envstr[255];
 584
 585         sernum = sbcommon_get_serial_number();
 586
 587         printf("\nSetting up environment for filesystem recovery\n");
 588         /*
 589          * Setup default bootargs
 590          */
 591         memset(envstr, 0, 255);
 592
 593         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 594                 "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
 595                 sernum, sernum);
 596         setenv("bootargs", envstr);
 597
 598         /*
 599          * Setup Default boot command
 600          */
 601
 602         setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
 603                "fatload ide 0 8100000 pramdisk;"
 604                "bootm 8000000 8100000");
 605
 606         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 607                " please type fsrecover.sh<cr>\n");
 608
 609         return(1);
 610 }
 611
 612 U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
 613            "Set environment to factory defaults", "");
 614
 615 U_BOOT_CMD(karecover, 1, 1, karefRecover,
 616            "Set environment to allow for fs recovery", "");