board/ronetix/pm9263/pm9263.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
   7  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   8  */
   9
  10 #include <common.h>
  11 #include <linux/sizes.h>
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <asm/arch/at91sam9_smc.h>
  15 #include <asm/arch/at91_common.h>
  16 #include <asm/arch/at91_rstc.h>
  17 #include <asm/arch/at91_matrix.h>
  18 #include <asm/arch/clk.h>
  19 #include <asm/arch/gpio.h>
  20 #include <lcd.h>
  21 #include <atmel_lcdc.h>
  22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  23 #include <net.h>
  24 #endif
  25 #include <netdev.h>
  26 #include <asm/mach-types.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /* ------------------------------------------------------------------------- */
  31 /*
  32  * Miscelaneous platform dependent initialisations
  33  */
  34
  35 #ifdef CONFIG_CMD_NAND
  36 static void pm9263_nand_hw_init(void)
  37 {
  38         unsigned long csa;
  39         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
  40         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  41
  42         /* Enable CS3 */
  43         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  44         writel(csa, &matrix->csa[0]);
  45
  46         /* Configure SMC CS3 for NAND/SmartMedia */
  47         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  48                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  49                 &smc->cs[3].setup);
  50
  51         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  52                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  53                 &smc->cs[3].pulse);
  54
  55         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  56                 &smc->cs[3].cycle);
  57
  58         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  59                 AT91_SMC_MODE_EXNW_DISABLE |
  60 #ifdef CONFIG_SYS_NAND_DBW_16
  61                 AT91_SMC_MODE_DBW_16 |
  62 #else /* CONFIG_SYS_NAND_DBW_8 */
  63                 AT91_SMC_MODE_DBW_8 |
  64 #endif
  65                 AT91_SMC_MODE_TDF_CYCLE(2),
  66                 &smc->cs[3].mode);
  67
  68         /* Configure RDY/BSY */
  69         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  70
  71         /* Enable NandFlash */
  72         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  73 }
  74 #endif
  75
  76 #ifdef CONFIG_MACB
  77 static void pm9263_macb_hw_init(void)
  78 {
  79         /*
  80          * PB27 enables the 50MHz oscillator for Ethernet PHY
  81          * 1 - enable
  82          * 0 - disable
  83          */
  84         at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
  85         at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
  86
  87         at91_periph_clk_enable(ATMEL_ID_EMAC);
  88
  89         /*
  90          * Disable pull-up on:
  91          *      RXDV (PC25) => PHY normal mode (not Test mode)
  92          *      ERX0 (PE25) => PHY ADDR0
  93          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  94          *
  95          * PHY has internal pull-down
  96          */
  97
  98         at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
  99         at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
 100         at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
 101
 102         /* Re-enable pull-up */
 103         at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
 104         at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
 105         at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
 106
 107         at91_macb_hw_init();
 108 }
 109 #endif
 110
 111 #ifdef CONFIG_LCD
 112 vidinfo_t panel_info = {
 113         .vl_col =               240,
 114         .vl_row =               320,
 115         .vl_clk =               4965000,
 116         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
 117                                         ATMEL_LCDC_INVFRAME_INVERTED,
 118         .vl_bpix =              3,
 119         .vl_tft =               1,
 120         .vl_hsync_len =         5,
 121         .vl_left_margin =       1,
 122         .vl_right_margin =      33,
 123         .vl_vsync_len =         1,
 124         .vl_upper_margin =      1,
 125         .vl_lower_margin =      0,
 126         .mmio =                 ATMEL_BASE_LCDC,
 127 };
 128
 129 void lcd_enable(void)
 130 {
 131         at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
 132 }
 133
 134 void lcd_disable(void)
 135 {
 136         at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
 137 }
 138
 139 #ifdef CONFIG_LCD_IN_PSRAM
 140
 141 #define PSRAM_CRE_PIN   AT91_PIO_PORTB, 29
 142 #define PSRAM_CTRL_REG  (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
 143
 144 /* Initialize the PSRAM memory */
 145 static int pm9263_lcd_hw_psram_init(void)
 146 {
 147         unsigned long csa;
 148         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
 149         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 150
 151         /* Enable CS3  3.3v, no pull-ups */
 152         csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
 153                 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
 154
 155         writel(csa, &matrix->csa[1]);
 156
 157         /* Configure SMC1 CS0 for PSRAM - 16-bit */
 158         writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
 159                 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
 160                 &smc->cs[0].setup);
 161
 162         writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
 163                 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
 164                 &smc->cs[0].pulse);
 165
 166         writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
 167                 &smc->cs[0].cycle);
 168
 169         writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
 170                 &smc->cs[0].mode);
 171
 172         /* setup PB29 as output */
 173         at91_set_pio_output(PSRAM_CRE_PIN, 1);
 174
 175         at91_set_pio_value(PSRAM_CRE_PIN, 0);   /* set PSRAM_CRE_PIN to '0' */
 176
 177         /* PSRAM: write BCR */
 178         readw(PSRAM_CTRL_REG);
 179         readw(PSRAM_CTRL_REG);
 180         writew(1, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 181         writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
 182
 183         /* write RCR of the PSRAM */
 184         readw(PSRAM_CTRL_REG);
 185         readw(PSRAM_CTRL_REG);
 186         writew(0, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 187         /* set RCR; 0x10-async mode,0x90-page mode */
 188         writew(0x90, PSRAM_CTRL_REG);
 189
 190         /*
 191          * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
 192          * MT45W2M16B - CRE must be 0
 193          * MT45W2M16A - CRE must be 1
 194          */
 195         writew(0x1234, PHYS_PSRAM);
 196         writew(0x5678, PHYS_PSRAM + 2);
 197
 198         /* test if the chip is MT45W2M16B */
 199         if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
 200                 /* try with CRE=1 (MT45W2M16A) */
 201                 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
 202
 203                 /* write RCR of the PSRAM */
 204                 readw(PSRAM_CTRL_REG);
 205                 readw(PSRAM_CTRL_REG);
 206                 writew(0, PSRAM_CTRL_REG);      /* 0 - RCR,1 - BCR */
 207                 /* set RCR;0x10-async mode,0x90-page mode */
 208                 writew(0x90, PSRAM_CTRL_REG);
 209
 210
 211                 writew(0x1234, PHYS_PSRAM);
 212                 writew(0x5678, PHYS_PSRAM+2);
 213                 if ((readw(PHYS_PSRAM) != 0x1234)
 214                   || (readw(PHYS_PSRAM + 2) != 0x5678))
 215                         return 1;
 216
 217         }
 218
 219         /* Bus matrix */
 220         writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
 221         writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
 222
 223         return 0;
 224 }
 225 #endif
 226
 227 static void pm9263_lcd_hw_init(void)
 228 {
 229         at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* LCDVSYNC */
 230         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 231         at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 232         at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 233         at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 234         at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 235         at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 236         at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 237         at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 238         at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 239         at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 240         at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 241         at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 242         at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 243         at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 244         at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 245         at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 246         at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 247         at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 248         at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 249         at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 250         at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 251         at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 252
 253         at91_periph_clk_enable(ATMEL_ID_LCDC);
 254
 255         /* Power Control */
 256         at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
 257         at91_set_pio_value(AT91_PIO_PORTA, 22, 0);      /* power down */
 258
 259 #ifdef CONFIG_LCD_IN_PSRAM
 260         /* initialize te PSRAM */
 261         int stat = pm9263_lcd_hw_psram_init();
 262
 263         gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
 264 #else
 265         gd->fb_base = ATMEL_BASE_SRAM0;
 266 #endif
 267
 268 }
 269
 270 #ifdef CONFIG_LCD_INFO
 271 #include <nand.h>
 272 #include <version.h>
 273
 274 extern flash_info_t flash_info[];
 275
 276 void lcd_show_board_info(void)
 277 {
 278         ulong dram_size, nand_size, flash_size;
 279         int i;
 280         char temp[32];
 281
 282         lcd_printf ("%s\n", U_BOOT_VERSION);
 283         lcd_printf ("(C) 2009 Ronetix GmbH\n");
 284         lcd_printf ("support@ronetix.at\n");
 285         lcd_printf ("%s CPU at %s MHz",
 286                 CONFIG_SYS_AT91_CPU_NAME,
 287                 strmhz(temp, get_cpu_clk_rate()));
 288
 289         dram_size = 0;
 290         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 291                 dram_size += gd->bd->bi_dram[i].size;
 292
 293         nand_size = 0;
 294         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 295                 nand_size += get_nand_dev_by_index(i)->size;
 296
 297         flash_size = 0;
 298         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 299                 flash_size += flash_info[i].size;
 300
 301         lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
 302                         "4 MB PSRAM\n",
 303                 dram_size >> 20,
 304                 nand_size >> 20,
 305                 flash_size >> 20);
 306 }
 307 #endif /* CONFIG_LCD_INFO */
 308
 309 #endif /* CONFIG_LCD */
 310
 311 int board_early_init_f(void)
 312 {
 313         return 0;
 314 }
 315
 316 int board_init(void)
 317 {
 318         /* arch number of AT91SAM9263EK-Board */
 319         gd->bd->bi_arch_number = MACH_TYPE_PM9263;
 320
 321         /* adress of boot parameters */
 322         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 323
 324 #ifdef CONFIG_CMD_NAND
 325         pm9263_nand_hw_init();
 326 #endif
 327 #ifdef CONFIG_MACB
 328         pm9263_macb_hw_init();
 329 #endif
 330 #ifdef CONFIG_USB_OHCI_NEW
 331         at91_uhp_hw_init();
 332 #endif
 333 #ifdef CONFIG_LCD
 334         pm9263_lcd_hw_init();
 335 #endif
 336         return 0;
 337 }
 338
 339 int dram_init(void)
 340 {
 341         /* dram_init must store complete ramsize in gd->ram_size */
 342         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 343                                 PHYS_SDRAM_SIZE);
 344         return 0;
 345 }
 346
 347 int dram_init_banksize(void)
 348 {
 349         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 350         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 351
 352         return 0;
 353 }
 354
 355 #ifdef CONFIG_RESET_PHY_R
 356 void reset_phy(void)
 357 {
 358 }
 359 #endif
 360
 361 int board_eth_init(bd_t *bis)
 362 {
 363         int rc = 0;
 364 #ifdef CONFIG_MACB
 365         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
 366 #endif
 367         return rc;
 368 }
 369
 370 #ifdef CONFIG_DISPLAY_BOARDINFO
 371 int checkboard (void)
 372 {
 373         char *ss;
 374
 375         printf ("Board : Ronetix PM9263\n");
 376
 377         switch (gd->fb_base) {
 378         case PHYS_PSRAM:
 379                 ss = "(PSRAM)";
 380                 break;
 381
 382         case ATMEL_BASE_SRAM0:
 383                 ss = "(Internal SRAM)";
 384                 break;
 385
 386         default:
 387                 ss = "";
 388                 break;
 389         }
 390         printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
 391
 392         printf ("\n");
 393         return 0;
 394 }
 395 #endif