board/renesas/rsk7264/lowlevel_init.S

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011 Renesas Electronics Europe Ltd.
   4  * Copyright (C) 2008 Renesas Solutions Corp.
   5  * Copyright (C) 2008 Nobuhiro Iwamatsu
   6  *
   7  * Based on board/renesas/rsk7203/lowlevel_init.S
   8  */
   9 #include <config.h>
  10
  11 #include <asm/processor.h>
  12 #include <asm/macro.h>
  13
  14         .global lowlevel_init
  15
  16         .text
  17         .align  2
  18
  19 lowlevel_init:
  20         /* Cache setting */
  21         write32 CCR1_A ,CCR1_D
  22
  23         /* io_set_cpg */
  24         write8 STBCR3_A, STBCR3_D
  25         write8 STBCR4_A, STBCR4_D
  26         write8 STBCR5_A, STBCR5_D
  27         write8 STBCR6_A, STBCR6_D
  28         write8 STBCR7_A, STBCR7_D
  29         write8 STBCR8_A, STBCR8_D
  30
  31         /* ConfigurePortPins */
  32
  33         /* Leaving LED1 ON for sanity test */
  34         write16 PJCR1_A, PJCR1_D1
  35         write16 PJCR2_A, PJCR2_D
  36         write16 PJIOR0_A, PJIOR0_D1
  37         write16 PJDR0_A, PJDR0_D
  38         write16 PJPR0_A, PJPR0_D
  39
  40         /* Configure EN_PIN & RS_PIN */
  41         write16 PGCR2_A, PGCR2_D
  42         write16 PGIOR0_A, PGIOR0_D
  43
  44         /* Configure the port pins connected to UART */
  45         write16 PJCR1_A, PJCR1_D2
  46         write16 PJIOR0_A, PJIOR0_D2
  47
  48         /* Configure Operating Frequency */
  49         write16 WTCSR_A, WTCSR_D0
  50         write16 WTCSR_A, WTCSR_D1
  51         write16 WTCNT_A, WTCNT_D
  52
  53         /* Control of RESBANK */
  54         write16 IBNR_A, IBNR_D
  55         /* Enable SCIF3 module */
  56         write16 STBCR4_A, STBCR4_D
  57
  58         /* Set clock mode*/
  59         write16 FRQCR_A, FRQCR_D
  60
  61         /* Configure Bus And Memory */
  62 init_bsc_cs0:
  63
  64 pfc_settings:
  65         write16 PCCR2_A, PCCR2_D
  66         write16 PCCR1_A, PCCR1_D
  67         write16 PCCR0_A, PCCR0_D
  68
  69         write16 PBCR0_A, PBCR0_D
  70         write16 PBCR1_A, PBCR1_D
  71         write16 PBCR2_A, PBCR2_D
  72         write16 PBCR3_A, PBCR3_D
  73         write16 PBCR4_A, PBCR4_D
  74         write16 PBCR5_A, PBCR5_D
  75
  76         write16 PDCR0_A, PDCR0_D
  77         write16 PDCR1_A, PDCR1_D
  78         write16 PDCR2_A, PDCR2_D
  79         write16 PDCR3_A, PDCR3_D
  80
  81         write32 CS0WCR_A, CS0WCR_D
  82         write32 CS0BCR_A, CS0BCR_D
  83
  84 init_bsc_cs2:
  85         write16 PJCR0_A, PJCR0_D
  86         write32 CS2WCR_A, CS2WCR_D
  87
  88 init_sdram:
  89         write32 CS3BCR_A, CS3BCR_D
  90         write32 CS3WCR_A, CS3WCR_D
  91         write32 SDCR_A, SDCR_D
  92         write32 RTCOR_A, RTCOR_D
  93         write32 RTCSR_A, RTCSR_D
  94
  95         /* wait 200us */
  96         mov.l   REPEAT_D, r3
  97         mov     #0, r2
  98 repeat0:
  99         add     #1, r2
 100         cmp/hs  r3, r2
 101         bf      repeat0
 102         nop
 103
 104         mov.l   SDRAM_MODE, r1
 105         mov     #0, r0
 106         mov.l   r0, @r1
 107
 108         nop
 109         rts
 110
 111         .align 4
 112
 113 CCR1_A:         .long CCR1
 114 CCR1_D:         .long 0x0000090B
 115 FRQCR_A:        .long 0xFFFE0010
 116 FRQCR_D:        .word 0x1003
 117 .align 2
 118 STBCR3_A:       .long 0xFFFE0408
 119 STBCR3_D:       .long 0x00000002
 120 STBCR4_A:       .long 0xFFFE040C
 121 STBCR4_D:       .word 0x0000
 122 .align 2
 123 STBCR5_A:       .long 0xFFFE0410
 124 STBCR5_D:       .long 0x00000010
 125 STBCR6_A:       .long 0xFFFE0414
 126 STBCR6_D:       .long 0x00000002
 127 STBCR7_A:       .long 0xFFFE0418
 128 STBCR7_D:       .long 0x0000002A
 129 STBCR8_A:       .long 0xFFFE041C
 130 STBCR8_D:       .long 0x0000007E
 131 PJCR1_A:        .long 0xFFFE390C
 132 PJCR1_D1:       .word 0x0000
 133 PJCR1_D2:       .word 0x0022
 134 PJCR2_A:        .long 0xFFFE390A
 135 PJCR2_D:        .word 0x0000
 136 .align 2
 137 PJIOR0_A:       .long 0xFFFE3912
 138 PJIOR0_D1:      .word 0x0FC0
 139 PJIOR0_D2:      .word 0x0FE0
 140 PJDR0_A:        .long 0xFFFE3916
 141 PJDR0_D:        .word 0x0FBF
 142 .align 2
 143 PJPR0_A:        .long 0xFFFE391A
 144 PJPR0_D:        .long 0x00000FBF
 145 PGCR2_A:        .long 0xFFFE38CA
 146 PGCR2_D:        .word 0x0000
 147 .align 2
 148 PGIOR0_A:       .long 0xFFFE38D2
 149 PGIOR0_D:       .word 0x03F0
 150 .align 2
 151 WTCSR_A:        .long 0xFFFE0000
 152 WTCSR_D0:       .word 0x0000
 153 WTCSR_D1:       .word 0x0000
 154 WTCNT_A:        .long 0xFFFE0002
 155 WTCNT_D:        .word 0x0000
 156 .align 2
 157 PCCR0_A:        .long 0xFFFE384E
 158 PDCR0_A:        .long 0xFFFE386E
 159 PDCR1_A:        .long 0xFFFE386C
 160 PDCR2_A:        .long 0xFFFE386A
 161 PDCR3_A:        .long 0xFFFE3868
 162 PBCR0_A:        .long 0xFFFE382E
 163 PBCR1_A:        .long 0xFFFE382C
 164 PBCR2_A:        .long 0xFFFE382A
 165 PBCR3_A:        .long 0xFFFE3828
 166 PBCR4_A:        .long 0xFFFE3826
 167 PBCR5_A:        .long 0xFFFE3824
 168 PCCR0_D:        .word 0x1111
 169 PDCR0_D:        .word 0x1111
 170 PDCR1_D:        .word 0x1111
 171 PDCR2_D:        .word 0x1111
 172 PDCR3_D:        .word 0x1111
 173 PBCR0_D:        .word 0x1110
 174 PBCR1_D:        .word 0x1111
 175 PBCR2_D:        .word 0x1111
 176 PBCR3_D:        .word 0x1111
 177 PBCR4_D:        .word 0x1111
 178 PBCR5_D:        .word 0x0111
 179 .align 2
 180 CS0WCR_A:       .long 0xFFFC0028
 181 CS0WCR_D:       .long 0x00000B41
 182 CS0BCR_A:       .long 0xFFFC0004
 183 CS0BCR_D:       .long 0x10000400
 184 PJCR0_A:        .long 0xFFFE390E
 185 PJCR0_D:        .word 0x3300
 186 .align 2
 187 CS2WCR_A:       .long 0xFFFC0030
 188 CS2WCR_D:       .long 0x00000B01
 189 PCCR2_A:        .long 0xFFFE384A
 190 PCCR2_D:        .word 0x0001
 191 .align 2
 192 PCCR1_A:        .long 0xFFFE384C
 193 PCCR1_D:        .word 0x1111
 194 .align 2
 195 CS3BCR_A:       .long 0xFFFC0010
 196 CS3BCR_D:       .long 0x00004400
 197 CS3WCR_A:       .long 0xFFFC0034
 198 CS3WCR_D:       .long 0x0000288A
 199 SDCR_A:         .long 0xFFFC004C
 200 SDCR_D:         .long 0x00000812
 201 RTCOR_A:        .long 0xFFFC0058
 202 RTCOR_D:        .long 0xA55A0046
 203 RTCSR_A:        .long 0xFFFC0050
 204 RTCSR_D:        .long 0xA55A0010
 205 IBNR_A:         .long 0xFFFE080E
 206 IBNR_D: .word 0x0000
 207 .align 2
 208 SDRAM_MODE:     .long 0xFFFC5040
 209 REPEAT_D:       .long 0x00000085