2 * board/renesas/porter/porter.c
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 * Copyright (C) 2015 Cogent Embedded, Inc.
7 * SPDX-License-Identifier: GPL-2.0
13 #include <dm/platform_data/serial_sh.h>
14 #include <environment.h>
15 #include <asm/processor.h>
16 #include <asm/mach-types.h>
18 #include <linux/errno.h>
19 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/rmobile.h>
22 #include <asm/arch/rcar-mstp.h>
23 #include <asm/arch/sh_sdhi.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #define CLK2MHZ(clk) (clk / 1000 / 1000)
35 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
36 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
40 writel(0xA5A5A500, &rwdt->rwtcsra);
41 writel(0xA5A5A500, &swdt->swtcsra);
43 /* CPU frequency setting. Set to 1.5GHz */
44 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
45 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
51 #define TMU0_MSTP125 BIT(25)
53 #define SD2CKCR 0xE615026C
54 #define SD_97500KHZ 0x7
56 int board_early_init_f(void)
58 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
61 * SD0 clock is set to 97.5MHz by default.
62 * Set SD2 to the 97.5MHz as well.
64 writel(SD_97500KHZ, SD2CKCR);
69 #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
76 /* Force ethernet PHY out of reset */
77 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
78 gpio_direction_output(ETHERNET_PHY_RESET, 0);
80 gpio_direction_output(ETHERNET_PHY_RESET, 1);
87 if (fdtdec_setup_memory_size() != 0)
93 int dram_init_banksize(void)
95 fdtdec_setup_memory_banksize();
100 /* porter has KSZ8041RNLI */
101 #define PHY_CONTROL1 0x1E
102 #define PHY_LED_MODE 0xC0000
103 #define PHY_LED_MODE_ACK 0x4000
104 int board_phy_config(struct phy_device *phydev)
106 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
107 ret &= ~PHY_LED_MODE;
108 ret |= PHY_LED_MODE_ACK;
109 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
114 void reset_cpu(ulong addr)
117 const u8 pmic_bus = 6;
118 const u8 pmic_addr = 0x5a;
122 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
126 ret = dm_i2c_read(dev, 0x13, &data, 1);
132 ret = dm_i2c_write(dev, 0x13, &data, 1);
137 enum env_location env_get_location(enum env_operation op, int prio)
139 const u32 load_magic = 0xb33fc0de;
141 /* Block environment access if loaded using JTAG */
142 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
149 return ENVL_SPI_FLASH;