board/omap2420h4/omap2420h4.c

   1 /*
   2  * (C) Copyright 2004
   3  * Texas Instruments, <www.ti.com>
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24 #include <common.h>
  25 #include <asm/arch/omap2420.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/bits.h>
  28 #include <asm/arch/mux.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/sys_info.h>
  31 #include <asm/arch/mem.h>
  32 #include <i2c.h>
  33 #include <asm/mach-types.h>
  34 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
  35 #include <linux/mtd/nand.h>
  36 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
  37 #endif
  38
  39  void wait_for_command_complete(unsigned int wd_base);
  40
  41 /*******************************************************
  42  * Routine: delay
  43  * Description: spinning delay to use before udelay works
  44  ******************************************************/
  45 static inline void delay (unsigned long loops)
  46 {
  47         __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
  48                 "bne 1b":"=r" (loops):"0" (loops));
  49 }
  50
  51 /*****************************************
  52  * Routine: board_init
  53  * Description: Early hardware init.
  54  *****************************************/
  55 int board_init (void)
  56 {
  57         DECLARE_GLOBAL_DATA_PTR;
  58
  59         gpmc_init(); /* in SRAM or SDRM, finish GPMC */
  60
  61         gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;             /* board id for linux */
  62         gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);     /* adress of boot parameters */
  63
  64         return 0;
  65 }
  66
  67 /**********************************************************
  68  * Routine: try_unlock_sram()
  69  * Description: If chip is GP type, unlock the SRAM for
  70  *  general use.
  71  ***********************************************************/
  72 void try_unlock_sram(void)
  73 {
  74         int mode;
  75
  76         /* if GP device unlock device SRAM for general use */
  77         mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
  78         if (mode == GP_DEVICE) {
  79                 __raw_writel(0xFF, A_REQINFOPERM0);
  80                 __raw_writel(0xCFDE, A_READPERM0);
  81                 __raw_writel(0xCFDE, A_WRITEPERM0);
  82         }
  83 }
  84
  85 /**********************************************************
  86  * Routine: try_unlock_sram()
  87  * Description: If chip is GP type, unlock the SRAM for
  88  *  general use.
  89  ***********************************************************/
  90 void try_unlock_sram(void)
  91 {
  92         /* if GP device unlock device SRAM for general use */
  93         if (get_device_type() == GP_DEVICE) {
  94                 __raw_writel(0xFF, A_REQINFOPERM0);
  95                 __raw_writel(0xCFDE, A_READPERM0);
  96                 __raw_writel(0xCFDE, A_WRITEPERM0);
  97         }
  98 }
  99
 100 /**********************************************************
 101  * Routine: s_init
 102  * Description: Does early system init of muxing and clocks.
 103  * - Called path is with sram stack.
 104  **********************************************************/
 105 void s_init(void)
 106 {
 107         int in_sdram = running_in_sdram();
 108
 109         watchdog_init();
 110         set_muxconf_regs();
 111         delay(100);
 112         try_unlock_sram();
 113
 114         if(!in_sdram)
 115                 prcm_init();
 116
 117         peripheral_enable();
 118         icache_enable();
 119         if (!in_sdram)
 120                 sdrc_init();
 121 }
 122
 123 /*******************************************************
 124  * Routine: misc_init_r
 125  * Description: Init ethernet (done here so udelay works)
 126  ********************************************************/
 127 int misc_init_r (void)
 128 {
 129         ether_init(); /* better done here so timers are init'ed */
 130         return(0);
 131 }
 132
 133 /****************************************
 134  * Routine: watchdog_init
 135  * Description: Shut down watch dogs
 136  *****************************************/
 137 void watchdog_init(void)
 138 {
 139         /* There are 4 watch dogs.  1 secure, and 3 general purpose.
 140         * The ROM takes care of the secure one. Of the 3 GP ones,
 141         * 1 can reset us directly, the other 2 only generate MPU interrupts.
 142         */
 143         __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
 144         wait_for_command_complete(WD2_BASE);
 145         __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
 146
 147 #if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
 148         __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
 149         wait_for_command_complete(WD3_BASE);
 150         __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
 151
 152         __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
 153         wait_for_command_complete(WD4_BASE);
 154         __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
 155 #endif
 156 }
 157
 158 /******************************************************
 159  * Routine: wait_for_command_complete
 160  * Description: Wait for posting to finish on watchdog
 161  ******************************************************/
 162 void wait_for_command_complete(unsigned int wd_base)
 163 {
 164         int pending = 1;
 165         do {
 166                 pending = __raw_readl(wd_base+WWPS);
 167         } while (pending);
 168 }
 169
 170 /*******************************************************************
 171  * Routine:ether_init
 172  * Description: take the Ethernet controller out of reset and wait
 173  *                 for the EEPROM load to complete.
 174  ******************************************************************/
 175 void ether_init (void)
 176 {
 177 #ifdef CONFIG_DRIVER_LAN91C96
 178         int cnt = 20;
 179
 180         __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
 181
 182         __raw_writew(0x0, LAN_RESET_REGISTER);
 183         do {
 184                 __raw_writew(0x1, LAN_RESET_REGISTER);
 185                 udelay (100);
 186                 if (cnt == 0)
 187                         goto h4reset_err_out;
 188                 --cnt;
 189         } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
 190
 191         cnt = 20;
 192
 193         do {
 194                 __raw_writew(0x0, LAN_RESET_REGISTER);
 195                 udelay (100);
 196                 if (cnt == 0)
 197                         goto h4reset_err_out;
 198                 --cnt;
 199         } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
 200         udelay (1000);
 201
 202         *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
 203         udelay (1000);
 204
 205         h4reset_err_out:
 206         return;
 207 #endif
 208 }
 209
 210 /**********************************************
 211  * Routine: dram_init
 212  * Description: sets uboots idea of sdram size
 213  **********************************************/
 214 int dram_init (void)
 215 {
 216         DECLARE_GLOBAL_DATA_PTR;
 217         unsigned int size0=0,size1=0;
 218         u32 mtype, btype, rev, cpu;
 219         u8 chg_on = 0x5; /* enable charge of back up battery */
 220         u8 vmode_on = 0x8C;
 221         #define NOT_EARLY 0
 222
 223         i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
 224
 225         btype = get_board_type();
 226         mtype = get_mem_type();
 227         rev = get_cpu_rev();
 228         cpu = get_cpu_type();
 229
 230         display_board_info(btype);
 231         if (btype == BOARD_H4_MENELAUS){
 232                 update_mux(btype,mtype); /* combo part on menelaus */
 233                 i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
 234                 i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
 235         }
 236
 237         if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
 238                 do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
 239         }
 240         size0 = get_sdr_cs_size(SDRC_CS0_OSET);
 241         size1 = get_sdr_cs_size(SDRC_CS1_OSET);
 242
 243         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 244         gd->bd->bi_dram[0].size = size0;
 245         if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
 246                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 247         else /* ES2 and above can remap at 32MB granularity */
 248                 gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
 249         gd->bd->bi_dram[1].size = size1;
 250
 251         return 0;
 252 }
 253
 254 /**********************************************************
 255  * Routine: set_muxconf_regs
 256  * Description: Setting up the configuration Mux registers
 257  *              specific to the hardware
 258  *********************************************************/
 259 void set_muxconf_regs (void)
 260 {
 261         muxSetupSDRC();
 262         muxSetupGPMC();
 263         muxSetupUsb0();
 264         muxSetupUart3();
 265         muxSetupI2C1();
 266         muxSetupUART1();
 267         muxSetupLCD();
 268         muxSetupCamera();
 269         muxSetupMMCSD();
 270         muxSetupTouchScreen();
 271         muxSetupHDQ();
 272 }
 273
 274 /*****************************************************************
 275  * Routine: peripheral_enable
 276  * Description: Enable the clks & power for perifs (GPT2, UART1,...)
 277  ******************************************************************/
 278 void peripheral_enable(void)
 279 {
 280         unsigned int v, if_clks=0, func_clks=0;
 281
 282         /* Enable GP2 timer.*/
 283         if_clks |= BIT4;
 284         func_clks |= BIT4;
 285         v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
 286         __raw_writel(v, CM_CLKSEL2_CORE);
 287         __raw_writel(0x1, CM_CLKSEL_WKUP);
 288
 289 #ifdef CFG_NS16550
 290         /* Enable UART1 clock */
 291         func_clks |= BIT21;
 292         if_clks |= BIT21;
 293 #endif
 294         v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;     /* Interface clocks on */
 295         __raw_writel(v,CM_ICLKEN1_CORE );
 296         v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
 297         __raw_writel(v, CM_FCLKEN1_CORE);
 298         delay(1000);
 299
 300 #ifndef KERNEL_UPDATED
 301         {
 302 #define V1 0xffffffff
 303 #define V2 0x00000007
 304
 305                 __raw_writel(V1, CM_FCLKEN1_CORE);
 306                 __raw_writel(V2, CM_FCLKEN2_CORE);
 307                 __raw_writel(V1, CM_ICLKEN1_CORE);
 308                 __raw_writel(V1, CM_ICLKEN2_CORE);
 309         }
 310 #endif
 311 }
 312
 313 /****************************************
 314  * Routine: muxSetupUsb0   (ostboot)
 315  * Description: Setup usb muxing
 316  *****************************************/
 317 void muxSetupUsb0(void)
 318 {
 319         volatile uint8   *MuxConfigReg;
 320         volatile uint32  *otgCtrlReg;
 321
 322         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
 323         *MuxConfigReg &= (uint8)(~0x1F);
 324
 325         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
 326         *MuxConfigReg &= (uint8)(~0x1F);
 327
 328         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
 329         *MuxConfigReg &= (uint8)(~0x1F);
 330
 331         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
 332         *MuxConfigReg &= (uint8)(~0x1F);
 333
 334         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
 335         *MuxConfigReg &= (uint8)(~0x1F);
 336
 337         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
 338         *MuxConfigReg &= (uint8)(~0x1F);
 339
 340         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
 341         *MuxConfigReg &= (uint8)(~0x1F);
 342
 343         /* setup for USB VBus detection */
 344         otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
 345         *otgCtrlReg |= 0x00040000; /* bit 18 */
 346 }
 347
 348 /****************************************
 349  * Routine: muxSetupUart3   (ostboot)
 350  * Description: Setup uart3 muxing
 351  *****************************************/
 352 void muxSetupUart3(void)
 353 {
 354         volatile uint8 *MuxConfigReg;
 355
 356         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
 357         *MuxConfigReg &= (uint8)(~0x1F);
 358
 359         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
 360         *MuxConfigReg &= (uint8)(~0x1F);
 361 }
 362
 363 /****************************************
 364  * Routine: muxSetupI2C1   (ostboot)
 365  * Description: Setup i2c muxing
 366  *****************************************/
 367 void muxSetupI2C1(void)
 368 {
 369         volatile unsigned char  *MuxConfigReg;
 370
 371         /* I2C1 Clock pin configuration, PIN = M19 */
 372         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
 373         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 374
 375         /* I2C1 Data pin configuration, PIN = L15 */
 376         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
 377         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 378
 379         /* Pull-up required on data line */
 380         /* external pull-up already present. */
 381         /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
 382 }
 383
 384 /****************************************
 385  * Routine: muxSetupUART1  (ostboot)
 386  * Description: Set up uart1 muxing
 387  *****************************************/
 388 void muxSetupUART1(void)
 389 {
 390         volatile unsigned char  *MuxConfigReg;
 391
 392         /* UART1_CTS pin configuration, PIN = D21 */
 393         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
 394         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 395
 396         /* UART1_RTS pin configuration, PIN = H21 */
 397         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
 398         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 399
 400         /* UART1_TX pin configuration, PIN = L20 */
 401         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
 402         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 403
 404         /* UART1_RX pin configuration, PIN = T21 */
 405         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
 406         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 407 }
 408
 409 /****************************************
 410  * Routine: muxSetupLCD   (ostboot)
 411  * Description: Setup lcd muxing
 412  *****************************************/
 413 void muxSetupLCD(void)
 414 {
 415         volatile unsigned char  *MuxConfigReg;
 416
 417         /* LCD_D0 pin configuration, PIN = Y7  */
 418         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
 419         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 420
 421         /* LCD_D1 pin configuration, PIN = P10 */
 422         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
 423         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 424
 425         /* LCD_D2 pin configuration, PIN = V8  */
 426         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
 427         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 428
 429         /* LCD_D3 pin configuration, PIN = Y8  */
 430         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
 431         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 432
 433         /* LCD_D4 pin configuration, PIN = W8  */
 434         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
 435         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 436
 437         /* LCD_D5 pin configuration, PIN = R10 */
 438         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
 439         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 440
 441         /* LCD_D6 pin configuration, PIN = Y9  */
 442         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
 443         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 444
 445         /* LCD_D7 pin configuration, PIN = V9  */
 446         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
 447         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 448
 449         /* LCD_D8 pin configuration, PIN = W9  */
 450         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
 451         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 452
 453         /* LCD_D9 pin configuration, PIN = P11 */
 454         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
 455         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 456
 457         /* LCD_D10 pin configuration, PIN = V10 */
 458         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
 459         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 460
 461         /* LCD_D11 pin configuration, PIN = Y10 */
 462         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
 463         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 464
 465         /* LCD_D12 pin configuration, PIN = W10 */
 466         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
 467         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 468
 469         /* LCD_D13 pin configuration, PIN = R11 */
 470         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
 471         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 472
 473         /* LCD_D14 pin configuration, PIN = V11 */
 474         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
 475         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 476
 477         /* LCD_D15 pin configuration, PIN = W11 */
 478         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
 479         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 480
 481         /* LCD_D16 pin configuration, PIN = P12 */
 482         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
 483         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 484
 485         /* LCD_D17 pin configuration, PIN = R12 */
 486         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
 487         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 488
 489         /* LCD_PCLK pin configuration,   PIN = W6   */
 490         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
 491         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 492
 493         /* LCD_VSYNC pin configuration,  PIN = V7  */
 494         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
 495         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 496
 497         /* LCD_HSYNC pin configuration,  PIN = Y6  */
 498         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
 499         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 500
 501         /* LCD_ACBIAS pin configuration, PIN = W7 */
 502         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
 503         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 504 }
 505
 506 /****************************************
 507  * Routine: muxSetupCamera  (ostboot)
 508  * Description: Setup camera muxing
 509  *****************************************/
 510 void muxSetupCamera(void)
 511 {
 512         volatile unsigned char  *MuxConfigReg;
 513
 514         /* CAMERA_RSTZ  pin configuration, PIN = Y16 */
 515         /* CAM_RST is connected through the I2C IO expander.*/
 516         /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
 517         /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled   */
 518
 519         /* CAMERA_XCLK  pin configuration, PIN = U3 */
 520         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
 521         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 522
 523         /* CAMERA_LCLK  pin configuration, PIN = V5 */
 524         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
 525         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 526
 527         /* CAMERA_VSYNC pin configuration, PIN = U2 */
 528         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
 529                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 530
 531         /* CAMERA_HSYNC pin configuration, PIN = T3 */
 532         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
 533                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 534
 535         /* CAMERA_DAT0 pin configuration, PIN = T4 */
 536         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
 537                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 538
 539         /* CAMERA_DAT1 pin configuration, PIN = V2 */
 540         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
 541                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 542
 543         /* CAMERA_DAT2 pin configuration, PIN = V3 */
 544         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
 545                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 546
 547         /* CAMERA_DAT3 pin configuration, PIN = U4 */
 548         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
 549                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 550
 551         /* CAMERA_DAT4 pin configuration, PIN = W2 */
 552         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
 553                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 554
 555         /* CAMERA_DAT5 pin configuration, PIN = V4 */
 556         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
 557                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 558
 559         /* CAMERA_DAT6 pin configuration, PIN = W3 */
 560         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
 561                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 562
 563         /* CAMERA_DAT7 pin configuration, PIN = Y2 */
 564         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
 565                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 566
 567         /* CAMERA_DAT8 pin configuration, PIN = Y4 */
 568         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
 569                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 570
 571         /* CAMERA_DAT9 pin configuration, PIN = V6 */
 572         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
 573                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 574 }
 575
 576 /****************************************
 577  * Routine: muxSetupMMCSD (ostboot)
 578  * Description: set up MMC muxing
 579  *****************************************/
 580 void muxSetupMMCSD(void)
 581 {
 582         volatile unsigned char  *MuxConfigReg;
 583
 584         /* SDMMC_CLKI pin configuration,  PIN = H15 */
 585         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
 586                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 587
 588         /* SDMMC_CLKO pin configuration,  PIN = G19 */
 589         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
 590                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 591
 592         /* SDMMC_CMD pin configuration,   PIN = H18 */
 593         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
 594                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 595         /* External pull-ups are present. */
 596         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 597
 598         /* SDMMC_DAT0 pin configuration,  PIN = F20 */
 599         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
 600                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 601         /* External pull-ups are present. */
 602         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 603
 604         /* SDMMC_DAT1 pin configuration,  PIN = H14 */
 605         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
 606                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 607         /* External pull-ups are present. */
 608         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 609
 610         /* SDMMC_DAT2 pin configuration,  PIN = E19 */
 611         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
 612                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 613         /* External pull-ups are present. */
 614         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 615
 616         /* SDMMC_DAT3 pin configuration,  PIN = D19 */
 617         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
 618                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 619         /* External pull-ups are present. */
 620         /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 621
 622         /* SDMMC_DDIR0 pin configuration, PIN = F19 */
 623         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
 624                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 625
 626         /* SDMMC_DDIR1 pin configuration, PIN = E20 */
 627         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
 628                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 629
 630         /* SDMMC_DDIR2 pin configuration, PIN = F18 */
 631         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
 632                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 633
 634         /* SDMMC_DDIR3 pin configuration, PIN = E18 */
 635         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
 636                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 637
 638         /* SDMMC_CDIR pin configuration,  PIN = G18 */
 639         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
 640                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 641
 642         /* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
 643         /* MMC_CD for 2422IP=K1 */
 644         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
 645                                    *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 646
 647         /* MMC_WP pin configuration,      PIN = B4  */
 648         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
 649                                    *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 650 }
 651
 652 /******************************************
 653  * Routine: muxSetupTouchScreen (ostboot)
 654  * Description:  Set up touch screen muxing
 655  *******************************************/
 656 void muxSetupTouchScreen(void)
 657 {
 658         volatile unsigned char  *MuxConfigReg;
 659
 660         /* SPI1_CLK pin configuration,  PIN = U18 */
 661         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
 662                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 663
 664         /* SPI1_MOSI pin configuration, PIN = V20 */
 665         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
 666                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 667
 668         /* SPI1_MISO pin configuration, PIN = T18 */
 669         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
 670                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 671
 672         /* SPI1_nCS0 pin configuration, PIN = U19 */
 673         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
 674                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 675
 676         /* PEN_IRQ pin configuration,   PIN = P20 */
 677         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
 678                                    *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 679 }
 680
 681 /****************************************
 682  * Routine: muxSetupHDQ (ostboot)
 683  * Description: setup 1wire mux
 684  *****************************************/
 685 void muxSetupHDQ(void)
 686 {
 687         volatile unsigned char  *MuxConfigReg;
 688
 689         /* HDQ_SIO pin configuration,  PIN = N18 */
 690         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
 691                                    *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 692 }
 693
 694 /***************************************************************
 695  * Routine: muxSetupGPMC (ostboot)
 696  * Description: Configures balls which cam up in protected mode
 697  ***************************************************************/
 698 void muxSetupGPMC(void)
 699 {
 700         volatile uint8 *MuxConfigReg;
 701         volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
 702
 703         /* gpmc_io_dir */
 704         *MCR = 0x19000000;
 705
 706         /* NOR FLASH CS0 */
 707         /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3       Pull/up - N/A */
 708         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
 709                                    *MuxConfigReg = 0x00 ;
 710
 711         /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3     Pull/up - N/A */
 712         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
 713                                    *MuxConfigReg = 0x01 ;
 714
 715         /* MPDB(Multi Port Debug Port) CS1 */
 716         /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1      Pull/up - N/A */
 717         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
 718                                    *MuxConfigReg = 0x00 ;
 719
 720         /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2      Pull/up - N/A */
 721         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
 722                                    *MuxConfigReg = 0x00 ;
 723 }
 724
 725 /****************************************************************
 726  * Routine: muxSetupSDRC  (ostboot)
 727  * Description: Configures balls which come up in protected mode
 728  ****************************************************************/
 729 void muxSetupSDRC(void)
 730 {
 731         volatile uint8 *MuxConfigReg;
 732
 733         /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1     Pull/up - N/A */
 734         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
 735                                    *MuxConfigReg = 0x00 ;
 736
 737         /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2      Pull/up - N/A */
 738         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
 739                                    *MuxConfigReg = 0x00 ;
 740
 741         /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3     Pull/up - N/A */
 742         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
 743                                    *MuxConfigReg = 0x00;
 744
 745         if (get_cpu_type() == CPU_2422) {
 746                 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
 747                                            *MuxConfigReg = 0x1b;
 748         }
 749 }
 750
 751 /*****************************************************************************
 752  * Routine: update_mux()
 753  * Description: Update balls which are different beween boards.  All should be
 754  *              updated to match functionaly.  However, I'm only updating ones
 755  *              which I'll be using for now.  When power comes into play they
 756  *              all need updating.
 757  *****************************************************************************/
 758 void update_mux(u32 btype,u32 mtype)
 759 {
 760         u32 cpu, base = OMAP2420_CTRL_BASE;
 761         cpu = get_cpu_type();
 762
 763         if (btype == BOARD_H4_MENELAUS) {
 764                 if (cpu == CPU_2420) {
 765                         /* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
 766                         __raw_writeb(0x3, base+0x30);
 767                         /* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
 768                         __raw_writeb(0x3, base+0xa3);
 769                         /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 770                         /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 771                         /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 772                         /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 773                         /* PIN = M1 (HSUSBOTG) */
 774                         /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 775                         __raw_writeb(0x3, base+0x9d);
 776                         /* PIN = U32, (WLAN_CLKREQ) */
 777                         /* PIN = Y11, WLAN */
 778                         /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 779                         __raw_writeb(0x3, base+0xe7);
 780                         /* PIN = AA8, mDOC */
 781                         /* PIN = AA10, BT */
 782                         /* PIN = AA13, WLAN */
 783                         /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 784                         __raw_writeb(0x3, base+0x10e);
 785                         /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 786                         __raw_writeb(0x3, base+0x110);
 787                         /* PIN = J15 HHUSB */
 788                         /* PIN = H19 HSUSB */
 789                         /* PIN = W13, P13, R13, W16 ... */
 790                         /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 791                         __raw_writeb(0x3, base+0xde);
 792                         /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 793                         __raw_writeb(0x0, base+0x12c);
 794                         /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 795                         __raw_writeb(0x0, base+0x136);
 796                 } else if (cpu == CPU_2422) {
 797                         /* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
 798                         /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 799                         /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 800                         /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 801                         /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 802                         __raw_writeb(0x0, base+0x92);
 803                         /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 804                         /* PIN = M1 (HSUSBOTG) */
 805                         /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 806                         __raw_writeb(0x3, base+0x10c);
 807                         /* PIN = U32, (WLAN_CLKREQ) */
 808                         /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 809                         __raw_writeb(0x3, base+0x30);
 810                         /* PIN = AA8, mDOC */
 811                         /* PIN = AA10, BT */
 812                         /* PIN = AA12, WLAN */
 813                         /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 814                         __raw_writeb(0x3, base+0x10e);
 815                         /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 816                         __raw_writeb(0x3, base+0x110);
 817                         /* PIN = J15 HHUSB */
 818                         /* PIN = H19 HSUSB */
 819                         /* PIN = W13, P13, R13, W16 ... */
 820                         /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 821                         __raw_writeb(0x3, base+0xde);
 822                         /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 823                         __raw_writeb(0x0, base+0x12c);
 824                         /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 825                         __raw_writeb(0x0, base+0x136);
 826                 }
 827
 828         } else if (btype == BOARD_H4_SDP) {
 829                 if (cpu == CPU_2420) {
 830                         /* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
 831                         /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 832                         /* Pin = Y11 VLNQ */
 833                         /* Pin = AA4 VLNQ */
 834                         /* Pin = AA6 VLNQ */
 835                         /* Pin = AA8 VLNQ */
 836                         /* Pin = AA10 VLNQ */
 837                         /* Pin = AA12 VLNQ */
 838                         /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 839                         __raw_writeb(0x3, base+0x10e);
 840                         /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 841                         __raw_writeb(0x3, base+0x110);
 842                         /* PIN = J15 MDOC_nDMAREQ */
 843                         /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 844                         __raw_writeb(0x3, base+0x114);
 845                         /* PIN = W13, V12, P13, R13, W19, W16 ... */
 846                         /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
 847                 } else if (cpu == CPU_2422) {
 848                         /* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
 849                         /* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
 850                         /* Pin = Y11 VLNQ */
 851                         /* Pin = AA4 VLNQ */
 852                         /* Pin = AA6 VLNQ */
 853                         /* Pin = AA8 VLNQ */
 854                         /* Pin = AA10 VLNQ */
 855                         /* Pin = AA12 VLNQ */
 856                         /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 857                         __raw_writeb(0x3, base+0x10e);
 858                         /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 859                         __raw_writeb(0x3, base+0x110);
 860                         /* PIN = J15 MDOC_nDMAREQ */
 861                         /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 862                         __raw_writeb(0x3, base+0x114);
 863                         /* PIN = W13, V12, P13, R13, W19, W16 ... */
 864                         /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
 865                 }
 866         }
 867 }
 868
 869 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 870 void nand_init(void)
 871 {
 872     extern flash_info_t flash_info[];
 873
 874     nand_probe(CFG_NAND_ADDR);
 875     if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 876                 print_size(nand_dev_desc[0].totlen, "\n");
 877     }
 878
 879 #ifdef CFG_JFFS2_MEM_NAND
 880     flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
 881     flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2;      /* only read kernel single meg partition */
 882         flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024;   /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
 883     flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
 884 #endif
 885 }
 886 #endif