1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 Keymile AG
4 * Valentin Longchamp <valentin.longchamp@keymile.com>
9 #include <linux/bitops.h>
14 /* QRIO ID register offset */
15 #define ID_REV_OFF 0x00
17 /* QRIO GPIO register offsets */
18 #define DIRECT_OFF 0x18
23 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
24 u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
26 printf("QRIO: id = %u, revision = %u\n",
27 (id_rev >> 8) & 0xff, id_rev & 0xff);
30 #define SLFTEST_OFF 0x06
32 bool qrio_get_selftest_pin(void)
36 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
38 slftest = in_8(qrio_base + SLFTEST_OFF);
40 return (slftest & 1) > 0;
43 #define BPRTH_OFF 0x04
45 bool qrio_get_pgy_pres_pin(void)
49 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
51 pgy_pres = in_8(qrio_base + BPRTH_OFF);
53 return (pgy_pres & 0x80) > 0;
56 int qrio_get_gpio(u8 port_off, u8 gpio_nr)
60 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
62 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
64 return (gprt >> gpio_nr) & 1U;
67 void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
71 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
75 gprt = in_be32(qrio_base + port_off + GPRT_OFF);
81 out_be32(qrio_base + port_off + GPRT_OFF, gprt);
84 void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
88 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
92 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
94 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
96 qrio_set_gpio(port_off, gpio_nr, value);
99 void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
103 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
105 mask = 1U << gpio_nr;
107 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
109 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
112 void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
116 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
118 mask = 1U << gpio_nr;
120 direct = in_be32(qrio_base + port_off + DIRECT_OFF);
122 /* set to output -> GPIO drives low */
125 /* set to input -> GPIO floating */
128 out_be32(qrio_base + port_off + DIRECT_OFF, direct);
131 #define WDMASK_OFF 0x16
133 void qrio_wdmask(u8 bit, bool wden)
136 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
138 wdmask = in_be16(qrio_base + WDMASK_OFF);
141 wdmask |= (1 << bit);
143 wdmask &= ~(1 << bit);
145 out_be16(qrio_base + WDMASK_OFF, wdmask);
148 #define PRST_OFF 0x1a
150 void qrio_prst(u8 bit, bool en, bool wden)
153 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
155 qrio_wdmask(bit, wden);
157 prst = in_be16(qrio_base + PRST_OFF);
164 out_be16(qrio_base + PRST_OFF, prst);
167 #define PRSTCFG_OFF 0x1c
169 void qrio_prstcfg(u8 bit, u8 mode)
171 unsigned long prstcfg;
173 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
175 prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
177 for (i = 0; i < 2; i++) {
179 __set_bit(2 * bit + i, &prstcfg);
181 __clear_bit(2 * bit + i, &prstcfg);
184 out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
187 #define CTRLH_OFF 0x02
188 #define CTRLH_WRL_BOOT 0x01
189 #define CTRLH_WRL_UNITRUN 0x02
191 void qrio_set_leds(void)
194 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
196 /* set UNIT LED to RED and BOOT LED to ON */
197 ctrlh = in_8(qrio_base + CTRLH_OFF);
198 ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
199 out_8(qrio_base + CTRLH_OFF, ctrlh);
202 #define CTRLL_OFF 0x03
203 #define CTRLL_WRB_BUFENA 0x20
205 void qrio_enable_app_buffer(void)
208 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
210 /* enable application buffer */
211 ctrll = in_8(qrio_base + CTRLL_OFF);
212 ctrll |= (CTRLL_WRB_BUFENA);
213 out_8(qrio_base + CTRLL_OFF, ctrll);
216 #define REASON1_OFF 0x12
217 #define REASON1_CPUWD 0x01
219 void qrio_cpuwd_flag(bool flag)
222 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
224 reason1 = in_8(qrio_base + REASON1_OFF);
226 reason1 |= REASON1_CPUWD;
228 reason1 &= ~REASON1_CPUWD;
229 out_8(qrio_base + REASON1_OFF, reason1);
232 #define REASON0_OFF 0x13
233 #define REASON0_SWURST 0x80
234 #define REASON0_CPURST 0x40
235 #define REASON0_BPRST 0x20
236 #define REASON0_COPRST 0x10
237 #define REASON0_SWCRST 0x08
238 #define REASON0_WDRST 0x04
239 #define REASON0_KBRST 0x02
240 #define REASON0_POWUP 0x01
242 (REASON0_POWUP | REASON0_COPRST | REASON0_KBRST |\
243 REASON0_BPRST | REASON0_SWURST | REASON0_WDRST)
244 #define CORE_RESET ((REASON1_CPUWD << 8) | REASON0_SWCRST)
246 bool qrio_reason_unitrst(void)
249 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
251 reason = in_be16(qrio_base + REASON1_OFF);
253 return (reason & UNIT_RESET) > 0;
256 #define RSTCFG_OFF 0x11
258 void qrio_uprstreq(u8 mode)
261 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
263 rstcfg = in_8(qrio_base + RSTCFG_OFF);
265 if (mode & UPREQ_CORE_RST)
266 rstcfg |= UPREQ_CORE_RST;
268 rstcfg &= ~UPREQ_CORE_RST;
270 out_8(qrio_base + RSTCFG_OFF, rstcfg);
273 /* Early bootcount memory area is avilable starting from QRIO3 Rev.2 */
274 #define QRIO3_ID 0x71
275 #define QRIO3_REV 0x02
276 #define EBOOTCNT_OFF 0x28
278 ulong early_bootcount_load(void)
280 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
281 u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
282 u8 id = (id_rev >> 8) & 0xff;
283 u8 rev = id_rev & 0xff;
286 if (id == QRIO3_ID && rev >= QRIO3_REV) {
287 ebootcount = in_be32(qrio_base + EBOOTCNT_OFF);
289 printf("QRIO: warning: early bootcount not supported, ");
290 printf("id = %u, rev = %u\n", id, rev);
296 void early_bootcount_store(ulong ebootcount)
298 void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE;
299 u16 id_rev = in_be16(qrio_base + ID_REV_OFF);
300 u8 id = (id_rev >> 8) & 0xff;
301 u8 rev = id_rev & 0xff;
303 if (id == QRIO3_ID && rev >= QRIO3_REV) {
304 out_be32(qrio_base + EBOOTCNT_OFF, ebootcount);
306 printf("QRIO: warning: early bootcount not supported, ");
307 printf("id = %u, rev = %u\n", id, rev);
311 /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
312 * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
313 * For I2C only the low state is activly driven and high state is pulled-up
314 * by a resistor. Therefore the deblock GPIOs are used
315 * -> as an active output to drive a low state
316 * -> as an open-drain input to have a pulled-up high state
319 /* By default deblock GPIOs are floating */
320 void i2c_deblock_gpio_cfg(void)
322 /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
323 qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT,
325 qrio_gpio_direction_input(KM_I2C_DEBLOCK_PORT,
328 qrio_set_gpio(KM_I2C_DEBLOCK_PORT,
329 KM_I2C_DEBLOCK_SCL, 0);
330 qrio_set_gpio(KM_I2C_DEBLOCK_PORT,
331 KM_I2C_DEBLOCK_SDA, 0);
334 void set_sda(int state)
336 qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT,
337 KM_I2C_DEBLOCK_SDA, state);
340 void set_scl(int state)
342 qrio_set_opendrain_gpio(KM_I2C_DEBLOCK_PORT,
343 KM_I2C_DEBLOCK_SCL, state);
348 return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,
354 return qrio_get_gpio(KM_I2C_DEBLOCK_PORT,