board/gdsys/405ep/io.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/ppc4xx-gpio.h>
  13
  14 #include <miiphy.h>
  15
  16 #include "405ep.h"
  17 #include <gdsys_fpga.h>
  18
  19 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  20 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  21 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  22
  23 #define PHYREG_CONTROL                          0
  24 #define PHYREG_PAGE_ADDRESS                     22
  25 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1    16
  26 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2    26
  27
  28 enum {
  29         UNITTYPE_CCD_SWITCH = 1,
  30 };
  31
  32 enum {
  33         HWVER_100 = 0,
  34         HWVER_110 = 1,
  35         HWVER_121 = 2,
  36         HWVER_122 = 3,
  37 };
  38
  39 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  40
  41 int misc_init_r(void)
  42 {
  43         /*
  44          * Note: DTT has been removed. Please use UCLASS_THERMAL.
  45          *
  46          * startup fans
  47          *
  48          * dtt_init();
  49          */
  50
  51         return 0;
  52 }
  53
  54 int configure_gbit_phy(unsigned char addr)
  55 {
  56         unsigned short value;
  57
  58         /* select page 2 */
  59         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  60                 PHYREG_PAGE_ADDRESS, 0x0002))
  61                 goto err_out;
  62         /* disable SGMII autonegotiation */
  63         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  64                 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
  65                 goto err_out;
  66         /* select page 0 */
  67         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  68                 PHYREG_PAGE_ADDRESS, 0x0000))
  69                 goto err_out;
  70         /* switch from powerdown to normal operation */
  71         if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  72                 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
  73                 goto err_out;
  74         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  75                 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
  76                 goto err_out;
  77         /* reset phy so settings take effect */
  78         if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  79                 PHYREG_CONTROL, 0x9140))
  80                 goto err_out;
  81
  82         return 0;
  83
  84 err_out:
  85         printf("Error writing to the PHY addr=%02x\n", addr);
  86         return -1;
  87 }
  88
  89 /*
  90  * Check Board Identity:
  91  */
  92 int checkboard(void)
  93 {
  94         char *s = getenv("serial#");
  95
  96         puts("Board: CATCenter Io");
  97
  98         if (s != NULL) {
  99                 puts(", serial# ");
 100                 puts(s);
 101         }
 102
 103         puts("\n");
 104
 105         return 0;
 106 }
 107
 108 static void print_fpga_info(void)
 109 {
 110         u16 versions;
 111         u16 fpga_version;
 112         u16 fpga_features;
 113         unsigned unit_type;
 114         unsigned hardware_version;
 115         unsigned feature_channels;
 116         unsigned feature_expansion;
 117
 118         FPGA_GET_REG(0, versions, &versions);
 119         FPGA_GET_REG(0, fpga_version, &fpga_version);
 120         FPGA_GET_REG(0, fpga_features, &fpga_features);
 121
 122         unit_type = (versions & 0xf000) >> 12;
 123         hardware_version = versions & 0x000f;
 124         feature_channels = fpga_features & 0x007f;
 125         feature_expansion = fpga_features & (1<<15);
 126
 127         puts("FPGA:  ");
 128
 129         switch (unit_type) {
 130         case UNITTYPE_CCD_SWITCH:
 131                 printf("CCD-Switch");
 132                 break;
 133
 134         default:
 135                 printf("UnitType %d(not supported)", unit_type);
 136                 break;
 137         }
 138
 139         switch (hardware_version) {
 140         case HWVER_100:
 141                 printf(" HW-Ver 1.00\n");
 142                 break;
 143
 144         case HWVER_110:
 145                 printf(" HW-Ver 1.10\n");
 146                 break;
 147
 148         case HWVER_121:
 149                 printf(" HW-Ver 1.21\n");
 150                 break;
 151
 152         case HWVER_122:
 153                 printf(" HW-Ver 1.22\n");
 154                 break;
 155
 156         default:
 157                 printf(" HW-Ver %d(not supported)\n",
 158                        hardware_version);
 159                 break;
 160         }
 161
 162         printf("       FPGA V %d.%02d, features:",
 163                 fpga_version / 100, fpga_version % 100);
 164
 165         printf(" %d channel(s)", feature_channels);
 166
 167         printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
 168 }
 169
 170 /*
 171  * setup Gbit PHYs
 172  */
 173 int last_stage_init(void)
 174 {
 175         unsigned int k;
 176
 177         print_fpga_info();
 178
 179         int retval;
 180         struct mii_dev *mdiodev = mdio_alloc();
 181         if (!mdiodev)
 182                 return -ENOMEM;
 183         strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
 184         mdiodev->read = bb_miiphy_read;
 185         mdiodev->write = bb_miiphy_write;
 186
 187         retval = mdio_register(mdiodev);
 188         if (retval < 0)
 189                 return retval;
 190
 191         for (k = 0; k < 32; ++k)
 192                 configure_gbit_phy(k);
 193
 194         /* take fpga serdes blocks out of reset */
 195         FPGA_SET_REG(0, quad_serdes_reset, 0);
 196
 197         return 0;
 198 }
 199
 200 void gd405ep_init(void)
 201 {
 202 }
 203
 204 void gd405ep_set_fpga_reset(unsigned state)
 205 {
 206         if (state) {
 207                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 208                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 209         } else {
 210                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 211                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 212         }
 213 }
 214
 215 void gd405ep_setup_hw(void)
 216 {
 217         /*
 218          * set "startup-finished"-gpios
 219          */
 220         gpio_write_bit(21, 0);
 221         gpio_write_bit(22, 1);
 222 }
 223
 224 int gd405ep_get_fpga_done(unsigned fpga)
 225 {
 226         return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
 227 }