3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
15 #include <gdsys_fpga.h>
17 #include "../common/osd.h"
19 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
20 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
21 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
22 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
24 #define LATCH2_MC2_PRESENT_N 0x0080
28 UNITTYPE_SERVER = 1<<1,
29 UNITTYPE_DISPLAYPORT = 1<<2,
59 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
64 * Note: DTT has been removed. Please use UCLASS_THERMAL.
74 static unsigned int get_hwver(void)
76 u16 latch3 = in_le16((void *)LATCH3_BASE);
78 return latch3 & 0x0003;
81 static unsigned int get_mc2_present(void)
83 u16 latch2 = in_le16((void *)LATCH2_BASE);
85 return !(latch2 & LATCH2_MC2_PRESENT_N);
88 static void print_fpga_info(unsigned dev)
94 unsigned hardware_version;
95 unsigned feature_rs232;
96 unsigned feature_audio;
97 unsigned feature_sysclock;
98 unsigned feature_ramconfig;
99 unsigned feature_carrier_speed;
100 unsigned feature_carriers;
101 unsigned feature_video_channels;
102 int fpga_state = get_fpga_state(dev);
104 printf("FPGA%d: ", dev);
106 FPGA_GET_REG(dev, versions, &versions);
107 FPGA_GET_REG(dev, fpga_version, &fpga_version);
108 FPGA_GET_REG(dev, fpga_features, &fpga_features);
110 hardware_version = versions & 0x000f;
113 && !((hardware_version == HWVER_101)
114 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
115 puts("not available\n");
116 if (fpga_state & FPGA_STATE_DONE_FAILED)
117 puts(" Waiting for FPGA-DONE timed out.\n");
118 if (fpga_state & FPGA_STATE_REFLECTION_FAILED)
119 puts(" FPGA reflection test failed.\n");
123 unit_type = (versions >> 4) & 0x000f;
124 hardware_version = versions & 0x000f;
125 feature_rs232 = fpga_features & (1<<11);
126 feature_audio = (fpga_features >> 9) & 0x0003;
127 feature_sysclock = (fpga_features >> 7) & 0x0003;
128 feature_ramconfig = (fpga_features >> 5) & 0x0003;
129 feature_carrier_speed = fpga_features & (1<<4);
130 feature_carriers = (fpga_features >> 2) & 0x0003;
131 feature_video_channels = fpga_features & 0x0003;
133 if (unit_type & UNITTYPE_MAIN)
134 printf("Mainchannel ");
136 printf("Videochannel ");
138 if (unit_type & UNITTYPE_SERVER)
139 printf("Serverside ");
143 if (unit_type & UNITTYPE_DISPLAYPORT)
144 printf("DisplayPort");
148 switch (hardware_version) {
150 printf(" HW-Ver 1.01\n");
154 printf(" HW-Ver 1.10-1.20\n");
158 printf(" HW-Ver 1.30\n");
162 printf(" HW-Ver 1.40-1.43\n");
166 printf(" HW-Ver 1.50\n");
170 printf(" HW-Ver 1.60-1.61\n");
174 printf(" HW-Ver 1.70\n");
178 printf(" HW-Ver %d(not supported)\n",
183 printf(" FPGA V %d.%02d, features:",
184 fpga_version / 100, fpga_version % 100);
186 printf(" %sRS232", feature_rs232 ? "" : "no ");
188 switch (feature_audio) {
190 printf(", no audio");
194 printf(", audio tx");
198 printf(", audio rx");
202 printf(", audio rx+tx");
206 printf(", audio %d(not supported)", feature_audio);
210 switch (feature_sysclock) {
212 printf(", clock 156.25 MHz");
216 printf(", clock %d(not supported)", feature_sysclock);
222 switch (feature_ramconfig) {
228 printf("RAM 32 bit DDR2");
232 printf("RAM 64 bit DDR2");
236 printf("RAM %d(not supported)", feature_ramconfig);
240 printf(", %d carrier(s) %s", feature_carriers,
241 feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
243 printf(", %d video channel(s)\n", feature_video_channels);
247 * Check Board Identity:
251 char *s = getenv("serial#");
255 puts("DLVision 10G");
267 int last_stage_init(void)
271 FPGA_GET_REG(0, versions, &versions);
274 if (get_mc2_present())
277 if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
280 if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
283 if (get_mc2_present() &&
284 (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
290 void gd405ep_init(void)
294 void gd405ep_set_fpga_reset(unsigned state)
297 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
298 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
300 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
301 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
305 void gd405ep_setup_hw(void)
308 * set "startup-finished"-gpios
310 gpio_write_bit(21, 0);
311 gpio_write_bit(22, 1);
314 int gd405ep_get_fpga_done(unsigned fpga)
316 return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);