board/gdsys/405ep/405ep.c

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/ppc4xx-gpio.h>
  13 #include <asm/global_data.h>
  14
  15 #include "405ep.h"
  16 #include <gdsys_fpga.h>
  17
  18 #define REFLECTION_TESTPATTERN 0xdede
  19 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  20
  21 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  22 #define REFLECTION_TESTREG reflection_low
  23 #else
  24 #define REFLECTION_TESTREG reflection_high
  25 #endif
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int get_fpga_state(unsigned dev)
  30 {
  31         return gd->arch.fpga_state[dev];
  32 }
  33
  34 int board_early_init_f(void)
  35 {
  36         unsigned k;
  37
  38         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  39                 gd->arch.fpga_state[k] = 0;
  40
  41         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  42         mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
  43         mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical */
  44         mtdcr(UIC0PR, 0xFFFFFF80);      /* set int polarities */
  45         mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
  46         mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest prio */
  47         mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  48
  49         /*
  50          * EBC Configuration Register: set ready timeout to 512 ebc-clks
  51          * -> ca. 15 us
  52          */
  53         mtebc(EBC0_CFG, 0xa8400000);    /* ebc always driven */
  54         return 0;
  55 }
  56
  57 int board_early_init_r(void)
  58 {
  59         unsigned k;
  60         unsigned ctr;
  61
  62         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
  63                 gd->arch.fpga_state[k] = 0;
  64
  65         /*
  66          * reset FPGA
  67          */
  68         gd405ep_init();
  69
  70         gd405ep_set_fpga_reset(1);
  71
  72         gd405ep_setup_hw();
  73
  74         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  75                 ctr = 0;
  76                 while (!gd405ep_get_fpga_done(k)) {
  77                         udelay(100000);
  78                         if (ctr++ > 5) {
  79                                 gd->arch.fpga_state[k] |=
  80                                         FPGA_STATE_DONE_FAILED;
  81                                 break;
  82                         }
  83                 }
  84         }
  85
  86         udelay(10);
  87
  88         gd405ep_set_fpga_reset(0);
  89
  90         for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
  91                 /*
  92                  * wait for fpga out of reset
  93                  */
  94                 ctr = 0;
  95                 while (1) {
  96                         u16 val;
  97
  98                         FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
  99
 100                         FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
 101                         if (val == REFLECTION_TESTPATTERN_INV)
 102                                 break;
 103
 104                         udelay(100000);
 105                         if (ctr++ > 5) {
 106                                 gd->arch.fpga_state[k] |=
 107                                         FPGA_STATE_REFLECTION_FAILED;
 108                                 break;
 109                         }
 110                 }
 111         }
 112
 113         return 0;
 114 }