board/freescale/t4rdb/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/mmu.h>
   8
   9 struct fsl_e_tlb_entry tlb_table[] = {
  10         /* TLB 0 - for temp stack in cache */
  11         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  12                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  13                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  14                       0, 0, BOOKE_PAGESZ_4K, 0),
  15         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  16                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  17                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  18                       0, 0, BOOKE_PAGESZ_4K, 0),
  19         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  20                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  21                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  25                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26                       0, 0, BOOKE_PAGESZ_4K, 0),
  27
  28         /* TLB 1 */
  29         /* *I*** - Covers boot page */
  30 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  31         /*
  32          * *I*G - L3SRAM. When L3 is used as 512K SRAM */
  33         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  34                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  35                         0, 0, BOOKE_PAGESZ_512K, 1),
  36 #else
  37         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  38                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  39                       0, 0, BOOKE_PAGESZ_4K, 1),
  40 #endif
  41
  42         /* *I*G* - CCSRBAR */
  43         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  44                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  45                       0, 1, BOOKE_PAGESZ_16M, 1),
  46
  47         /* *I*G* - Flash, localbus */
  48         /* This will be changed to *I*G* after relocation to RAM. */
  49         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  50                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  51                       0, 2, BOOKE_PAGESZ_256M, 1),
  52
  53 #ifndef CONFIG_SPL_BUILD
  54         /* *I*G* - PCI */
  55         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  56                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57                       0, 3, BOOKE_PAGESZ_1G, 1),
  58
  59         /* *I*G* - PCI */
  60         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  61                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  62                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  63                       0, 4, BOOKE_PAGESZ_256M, 1),
  64
  65         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  66                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  67                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68                       0, 5, BOOKE_PAGESZ_256M, 1),
  69
  70         /* *I*G* - PCI I/O */
  71         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  72                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73                       0, 6, BOOKE_PAGESZ_256K, 1),
  74
  75         /* Bman/Qman */
  76 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  77         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  78                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  79                       0, 9, BOOKE_PAGESZ_16M, 1),
  80         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  81                       CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  82                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  83                       0, 10, BOOKE_PAGESZ_16M, 1),
  84 #endif
  85 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  86         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  87                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  88                       0, 11, BOOKE_PAGESZ_16M, 1),
  89         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  90                       CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  91                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92                       0, 12, BOOKE_PAGESZ_16M, 1),
  93 #endif
  94 #endif
  95
  96 #ifdef CONFIG_SYS_DCSRBAR_PHYS
  97         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  98                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  99                       0, 13, BOOKE_PAGESZ_32M, 1),
 100 #endif
 101 #ifdef CONFIG_SYS_NAND_BASE
 102         /*
 103          * *I*G - NAND
 104          * entry 14 and 15 has been used hard coded, they will be disabled
 105          * in cpu_init_f, so we use entry 16 for nand.
 106          */
 107         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 108                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 109                       0, 16, BOOKE_PAGESZ_64K, 1),
 110 #endif
 111 #ifdef CONFIG_SYS_CPLD_BASE
 112         SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 113                       MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 114                       0, 17, BOOKE_PAGESZ_4K, 1),
 115 #endif
 116 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 117         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 118                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 119                       0, 18, BOOKE_PAGESZ_2G, 1)
 120 #endif
 121 };
 122
 123 int num_tlb_entries = ARRAY_SIZE(tlb_table);