1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2013 Freescale Semiconductor, Inc.
10 #include <fdt_support.h>
15 #include <asm/global_data.h>
16 #include <linux/compiler.h>
18 #include <asm/processor.h>
19 #include <asm/immap_85xx.h>
20 #include <asm/fsl_law.h>
21 #include <asm/fsl_serdes.h>
22 #include <asm/fsl_liodn.h>
26 #include "../common/vid.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 u8 get_hw_revision(void)
32 u8 ver = CPLD_READ(hw_ver);
47 struct cpu_type *cpu = gd->arch.cpu;
48 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
50 printf("Board: %sRDB, ", cpu->name);
51 printf("Board rev: %c CPLD ver: 0x%02x, boot from ",
52 get_hw_revision(), CPLD_READ(sw_ver));
61 reg = CPLD_READ(flash_csr);
63 if (reg & CPLD_BOOT_SEL) {
66 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
67 printf("NOR vBank%d\n", reg);
71 puts("SERDES Reference Clocks:\n");
72 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
73 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
78 int board_early_init_r(void)
80 const unsigned int flashbase = CFG_SYS_FLASH_BASE;
81 int flash_esel = find_tlb_idx((void *)flashbase, 1);
83 * Remap Boot flash + PROMJET region to caching-inhibited
84 * so that flash can be erased properly.
87 /* Flush d-cache and invalidate i-cache of any FLASH data */
90 if (flash_esel == -1) {
91 /* very unlikely unless something is messed up */
92 puts("Error: Could not find TLB for FLASH BASE\n");
93 flash_esel = 2; /* give our best effort to continue */
95 /* invalidate existing TLB entry for flash + promjet */
96 disable_tlb(flash_esel);
99 set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
100 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
101 0, flash_esel, BOOKE_PAGESZ_256M, 1);
104 * Adjust core voltage according to voltage ID
105 * This function changes I2C mux to channel 2.
108 printf("Warning: Adjusting core voltage failed.\n");
112 int misc_init_r(void)
116 /* Reset CS4315 PHY */
117 reg = CPLD_READ(reset_ctl);
118 reg |= CPLD_RSTCON_EDC_RST;
119 CPLD_WRITE(reset_ctl, reg);
121 /* Enable POR for boards revisions D and up */
122 if (get_hw_revision() >= 'D') {
123 reg = CPLD_READ(misc_csr);
124 reg |= CPLD_MISC_POR_EN;
125 CPLD_WRITE(misc_csr, reg);
131 int ft_board_setup(void *blob, struct bd_info *bd)
136 ft_cpu_setup(blob, bd);
138 base = env_get_bootm_low();
139 size = env_get_bootm_size();
141 fdt_fixup_memory(blob, (u64)base, (u64)size);
144 pci_of_setup(blob, bd);
147 fdt_fixup_liodn(blob);
148 fsl_fdt_fixup_dr_usb(blob, bd);
150 #ifdef CONFIG_SYS_DPAA_FMAN
151 fdt_fixup_board_fman_ethernet(blob);
152 fdt_fixup_board_enet(blob);
153 fdt_fixup_board_phy(blob);
159 ulong *cs4340_get_fw_addr(void)
161 ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
163 #ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
166 reg = CPLD_READ(flash_csr);
167 if (!(reg & CPLD_BOOT_SEL)) {
168 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
170 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
172 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
176 return (ulong *)cortina_fw_addr;