board/freescale/t104xrdb/t104xrdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <env.h>
   9 #include <fdt_support.h>
  10 #include <hwconfig.h>
  11 #include <init.h>
  12 #include <netdev.h>
  13 #include <linux/compiler.h>
  14 #include <asm/mmu.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17 #include <asm/immap_85xx.h>
  18 #include <asm/fsl_fdt.h>
  19 #include <asm/fsl_law.h>
  20 #include <asm/fsl_serdes.h>
  21 #include <asm/fsl_liodn.h>
  22 #include <fm_eth.h>
  23 #include "../common/sleep.h"
  24 #include "t104xrdb.h"
  25 #include "cpld.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int checkboard(void)
  30 {
  31         struct cpu_type *cpu = gd->arch.cpu;
  32         u8 sw;
  33
  34 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
  35         printf("Board: %sD4RDB\n", cpu->name);
  36 #else
  37         printf("Board: %sRDB\n", cpu->name);
  38 #endif
  39         printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
  40                CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  41
  42         sw = CPLD_READ(flash_ctl_status);
  43         sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  44
  45         printf("vBank: %d\n", sw);
  46
  47         return 0;
  48 }
  49
  50 int board_early_init_f(void)
  51 {
  52 #if defined(CONFIG_DEEP_SLEEP)
  53         if (is_warm_boot())
  54                 fsl_dp_disable_console();
  55 #endif
  56
  57         return 0;
  58 }
  59
  60 int board_early_init_r(void)
  61 {
  62 #ifdef CONFIG_SYS_FLASH_BASE
  63         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  64         int flash_esel = find_tlb_idx((void *)flashbase, 1);
  65
  66         /*
  67          * Remap Boot flash region to caching-inhibited
  68          * so that flash can be erased properly.
  69          */
  70
  71         /* Flush d-cache and invalidate i-cache of any FLASH data */
  72         flush_dcache();
  73         invalidate_icache();
  74
  75         if (flash_esel == -1) {
  76                 /* very unlikely unless something is messed up */
  77                 puts("Error: Could not find TLB for FLASH BASE\n");
  78                 flash_esel = 2; /* give our best effort to continue */
  79         } else {
  80                 /* invalidate existing TLB entry for flash */
  81                 disable_tlb(flash_esel);
  82         }
  83
  84         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  85                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  86                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  87 #endif
  88         return 0;
  89 }
  90
  91 int misc_init_r(void)
  92 {
  93         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  94         u32 srds_s1;
  95
  96         srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
  97
  98         printf("SERDES Reference : 0x%X\n", srds_s1);
  99
 100         /* select SGMII*/
 101         if (srds_s1 == 0x86)
 102                 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 103                                          MISC_CTL_SG_SEL);
 104
 105         /* select SGMII and Aurora*/
 106         if (srds_s1 == 0x8E)
 107                 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 108                                          MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
 109
 110 #if defined(CONFIG_TARGET_T1040D4RDB)
 111         if (hwconfig("qe-tdm")) {
 112                 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
 113                            MISC_MUX_QE_TDM);
 114                 printf("QECSR : 0x%02x, mux to qe-tdm\n",
 115                        CPLD_READ(sfp_ctl_status));
 116         }
 117         /* Mask all CPLD interrupt sources, except QSGMII interrupts */
 118         if (CPLD_READ(sw_ver) < 0x03) {
 119                 debug("CPLD SW version 0x%02x doesn't support int_mask\n",
 120                       CPLD_READ(sw_ver));
 121         } else {
 122                 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
 123                            ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
 124         }
 125 #endif
 126
 127         return 0;
 128 }
 129
 130 int ft_board_setup(void *blob, bd_t *bd)
 131 {
 132         phys_addr_t base;
 133         phys_size_t size;
 134
 135         ft_cpu_setup(blob, bd);
 136
 137         base = env_get_bootm_low();
 138         size = env_get_bootm_size();
 139
 140         fdt_fixup_memory(blob, (u64)base, (u64)size);
 141
 142 #ifdef CONFIG_PCI
 143         pci_of_setup(blob, bd);
 144 #endif
 145
 146         fdt_fixup_liodn(blob);
 147
 148 #ifdef CONFIG_HAS_FSL_DR_USB
 149         fsl_fdt_fixup_dr_usb(blob, bd);
 150 #endif
 151
 152 #ifdef CONFIG_SYS_DPAA_FMAN
 153         fdt_fixup_fman_ethernet(blob);
 154 #endif
 155
 156         if (hwconfig("qe-tdm"))
 157                 fdt_del_diu(blob);
 158         return 0;
 159 }