board/freescale/t104xrdb/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <hwconfig.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <asm/global_data.h>
  12 #include <asm/mmu.h>
  13 #include <fsl_ddr_sdram.h>
  14 #include <fsl_ddr_dimm_params.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/mpc85xx_gpio.h>
  17 #include <linux/delay.h>
  18 #include "ddr.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 void fsl_ddr_board_options(memctl_options_t *popts,
  23                                 dimm_params_t *pdimm,
  24                                 unsigned int ctrl_num)
  25 {
  26         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  27         ulong ddr_freq;
  28
  29         if (ctrl_num > 1) {
  30                 printf("Not supported controller number %d\n", ctrl_num);
  31                 return;
  32         }
  33         if (!pdimm->n_ranks)
  34                 return;
  35
  36         pbsp = udimms[0];
  37
  38         /* Get clk_adjust according to the board ddr
  39          * freqency and n_banks specified in board_specific_parameters table.
  40          */
  41         ddr_freq = get_ddr_freq(0) / 1000000;
  42         while (pbsp->datarate_mhz_high) {
  43                 if (pbsp->n_ranks == pdimm->n_ranks &&
  44                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  45                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  46                                 popts->clk_adjust = pbsp->clk_adjust;
  47                                 popts->wrlvl_start = pbsp->wrlvl_start;
  48                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  49                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  50                                 goto found;
  51                         }
  52                         pbsp_highest = pbsp;
  53                 }
  54                 pbsp++;
  55         }
  56
  57         if (pbsp_highest) {
  58                 printf("Error: board specific timing not found\n");
  59                 printf("for data rate %lu MT/s\n", ddr_freq);
  60                 printf("Trying to use the highest speed (%u) parameters\n",
  61                        pbsp_highest->datarate_mhz_high);
  62                 popts->clk_adjust = pbsp_highest->clk_adjust;
  63                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  64                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  65                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  66         } else {
  67                 panic("DIMM is not supported by this board");
  68         }
  69 found:
  70         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  71                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  72                 "wrlvl_ctrl_3 0x%x\n",
  73                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  74                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  75                 pbsp->wrlvl_ctl_3);
  76
  77         /*
  78          * Factors to consider for half-strength driver enable:
  79          *      - number of DIMMs installed
  80          */
  81 #ifdef CONFIG_SYS_FSL_DDR4
  82         popts->half_strength_driver_enable = 1;
  83         /* optimize cpo for erratum A-009942 */
  84         popts->cpo_sample = 0x59;
  85 #else
  86         popts->half_strength_driver_enable = 0;
  87 #endif
  88         /*
  89          * Write leveling override
  90          */
  91         popts->wrlvl_override = 1;
  92         popts->wrlvl_sample = 0xf;
  93
  94         /*
  95          * rtt and rtt_wr override
  96          */
  97         popts->rtt_override = 0;
  98
  99         /* Enable ZQ calibration */
 100         popts->zq_en = 1;
 101
 102         /* DHC_EN =1, ODT = 75 Ohm */
 103 #ifdef CONFIG_SYS_FSL_DDR4
 104         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
 105         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
 106                 DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
 107 #else
 108         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 109         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 110 #endif
 111 }
 112
 113 #if defined(CONFIG_DEEP_SLEEP)
 114 void board_mem_sleep_setup(void)
 115 {
 116         void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
 117
 118         /* does not provide HW signals for power management */
 119         clrbits_8(cpld_base + 0x17, 0x40);
 120         /* Disable MCKE isolation */
 121         gpio_set_value(2, 0);
 122         udelay(1);
 123 }
 124 #endif
 125
 126 int dram_init(void)
 127 {
 128         phys_size_t dram_size;
 129
 130 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 131         puts("Initializing....using SPD\n");
 132         dram_size = fsl_ddr_sdram();
 133 #else
 134         dram_size =  fsl_ddr_sdram_size();
 135 #endif
 136         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 137         dram_size *= 0x100000;
 138
 139 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 140         fsl_dp_resume();
 141 #endif
 142
 143         gd->ram_size = dram_size;
 144
 145         return 0;
 146 }