1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
5 * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
9 #include <clock_legacy.h>
11 #include <linux/ctype.h>
13 #include <stdio_dev.h>
15 #include <fsl_diu_fb.h>
16 #include "../common/qixis.h"
17 #include "../common/diu_ch7301.h"
19 #include "t1040qds_qixis.h"
24 * Note that we need to byte-swap the value before it's written to the AD
25 * register. So even though the registers don't look like they're in the same
26 * bit positions as they are on the MPC8610, the same value is written to the
27 * AD register on the MPC8610 and on the P1022.
29 #define AD_BYTE_F 0x10000000
30 #define AD_ALPHA_C_SHIFT 25
31 #define AD_BLUE_C_SHIFT 23
32 #define AD_GREEN_C_SHIFT 21
33 #define AD_RED_C_SHIFT 19
34 #define AD_PIXEL_S_SHIFT 16
35 #define AD_COMP_3_SHIFT 12
36 #define AD_COMP_2_SHIFT 8
37 #define AD_COMP_1_SHIFT 4
38 #define AD_COMP_0_SHIFT 0
40 void diu_set_pixel_clock(unsigned int pixclock)
42 unsigned long speed_ccb, temp;
45 speed_ccb = get_bus_freq(0);
46 temp = 1000000000 / pixclock;
48 pixval = speed_ccb / temp;
50 /* Program HDMI encoder */
51 /* Switch channel to DIU */
52 select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);
54 /* Set dispaly encoder */
55 ret = diu_set_dvi_encoder(temp);
57 puts("Failed to set DVI encoder\n");
61 /* Switch channel to default */
62 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
64 /* Program pixel clock */
65 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
66 ((pixval << PXCK_BITS_START) & PXCK_MASK));
68 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
69 ((pixval << PXCK_BITS_START) & PXCK_MASK));
72 int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
77 /*Route I2C4 to DIU system as HSYNC/VSYNC*/
78 sw = QIXIS_READ(brdcfg[5]);
79 QIXIS_WRITE(brdcfg[5],
80 ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
82 /*Configure Display ouput port as HDMI*/
83 sw = QIXIS_READ(brdcfg[15]);
84 QIXIS_WRITE(brdcfg[15],
85 ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
86 | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
88 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
89 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
90 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
91 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
92 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
94 printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
97 return fsl_diu_init(xres, yres, pixel_format, 0);