board/freescale/t102xqds/ddr.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <hwconfig.h>
  10 #include <asm/mmu.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <fsl_ddr_dimm_params.h>
  13 #include <asm/fsl_law.h>
  14 #include <asm/mpc85xx_gpio.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 struct board_specific_parameters {
  19         u32 n_ranks;
  20         u32 datarate_mhz_high;
  21         u32 rank_gb;
  22         u32 clk_adjust;
  23         u32 wrlvl_start;
  24         u32 wrlvl_ctl_2;
  25         u32 wrlvl_ctl_3;
  26 };
  27
  28 /*
  29  * datarate_mhz_high values need to be in ascending order
  30  */
  31 static const struct board_specific_parameters udimm0[] = {
  32         /*
  33          * memory controller 0
  34          *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
  35          * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
  36          */
  37 #if defined(CONFIG_SYS_FSL_DDR4)
  38         {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  39         {2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
  40         {1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
  41         {1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
  42         {1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
  43 #elif defined(CONFIG_SYS_FSL_DDR3)
  44         {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  45         {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  46         {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  47         {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  48         {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  49         {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  50 #else
  51 #error DDR type not defined
  52 #endif
  53         {}
  54 };
  55
  56 static const struct board_specific_parameters *udimms[] = {
  57         udimm0,
  58 };
  59
  60 void fsl_ddr_board_options(memctl_options_t *popts,
  61                            dimm_params_t *pdimm,
  62                            unsigned int ctrl_num)
  63 {
  64         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  65         ulong ddr_freq;
  66         struct cpu_type *cpu = gd->arch.cpu;
  67
  68         if (ctrl_num > 2) {
  69                 printf("Not supported controller number %d\n", ctrl_num);
  70                 return;
  71         }
  72         if (!pdimm->n_ranks)
  73                 return;
  74
  75         pbsp = udimms[0];
  76
  77         /* Get clk_adjust according to the board ddr freqency and n_banks
  78          * specified in board_specific_parameters table.
  79          */
  80         ddr_freq = get_ddr_freq(0) / 1000000;
  81         while (pbsp->datarate_mhz_high) {
  82                 if (pbsp->n_ranks == pdimm->n_ranks &&
  83                     (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  84                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  85                                 popts->clk_adjust = pbsp->clk_adjust;
  86                                 popts->wrlvl_start = pbsp->wrlvl_start;
  87                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  88                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  89                                 goto found;
  90                         }
  91                         pbsp_highest = pbsp;
  92                 }
  93                 pbsp++;
  94         }
  95
  96         if (pbsp_highest) {
  97                 printf("Error: board specific timing not found\n");
  98                 printf("for data rate %lu MT/s\n", ddr_freq);
  99                 printf("Trying to use the highest speed (%u) parameters\n",
 100                        pbsp_highest->datarate_mhz_high);
 101                 popts->clk_adjust = pbsp_highest->clk_adjust;
 102                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
 103                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
 104                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
 105         } else {
 106                 panic("DIMM is not supported by this board");
 107         }
 108 found:
 109         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
 110               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
 111         debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
 112               pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
 113         debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
 114
 115         /*
 116          * Factors to consider for half-strength driver enable:
 117          *      - number of DIMMs installed
 118          */
 119         popts->half_strength_driver_enable = 1;
 120         /*
 121          * Write leveling override
 122          */
 123         popts->wrlvl_override = 1;
 124         popts->wrlvl_sample = 0xf;
 125
 126         /*
 127          * rtt and rtt_wr override
 128          */
 129         popts->rtt_override = 0;
 130
 131         /* Enable ZQ calibration */
 132         popts->zq_en = 1;
 133
 134         /* DHC_EN =1, ODT = 75 Ohm */
 135 #ifdef CONFIG_SYS_FSL_DDR4
 136         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 137         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 138                           DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
 139 #else
 140         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 141         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 142
 143         /* optimize cpo for erratum A-009942 */
 144         popts->cpo_sample = 0x5f;
 145 #endif
 146
 147         /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
 148          * set DDR bus width to 32bit for T1023
 149          */
 150         if (cpu->soc_ver == SVR_T1023)
 151                 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 152
 153 #ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
 154         /* for DDR bus 32bit test on T1024 */
 155         popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 156 #endif
 157 }
 158
 159 #if defined(CONFIG_DEEP_SLEEP)
 160 void board_mem_sleep_setup(void)
 161 {
 162         void __iomem *qixis_base = (void *)QIXIS_BASE;
 163
 164         /* does not provide HW signals for power management */
 165         clrbits_8(qixis_base + 0x21, 0x2);
 166         /* Disable MCKE isolation */
 167         gpio_set_value(2, 0);
 168         udelay(1);
 169 }
 170 #endif
 171
 172 int dram_init(void)
 173 {
 174         phys_size_t dram_size;
 175
 176 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 177         puts("Initializing....using SPD\n");
 178         dram_size = fsl_ddr_sdram();
 179 #else
 180         /* DDR has been initialised by first stage boot loader */
 181         dram_size =  fsl_ddr_sdram_size();
 182 #endif
 183         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 184         dram_size *= 0x100000;
 185
 186 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 187         fsl_dp_resume();
 188 #endif
 189
 190         gd->ram_size = dram_size;
 191
 192         return 0;
 193 }