board/freescale/mx6sabreauto/mx6sabreauto.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   6  */
   7
   8 #include <common.h>
   9 #include <image.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include <env.h>
  19 #include <linux/errno.h>
  20 #include <asm/gpio.h>
  21 #include <asm/mach-imx/iomux-v3.h>
  22 #include <asm/mach-imx/mxc_i2c.h>
  23 #include <asm/mach-imx/boot_mode.h>
  24 #include <asm/mach-imx/spi.h>
  25 #include <mmc.h>
  26 #include <fsl_esdhc_imx.h>
  27 #include <miiphy.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <i2c.h>
  30 #include <input.h>
  31 #include <asm/arch/mxc_hdmi.h>
  32 #include <asm/mach-imx/video.h>
  33 #include <asm/arch/crm_regs.h>
  34 #include <pca953x.h>
  35 #include <power/pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include "../common/pfuze.h"
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  42         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  46         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  47         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51
  52 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  54         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  55
  56 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  57 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  58                         PAD_CTL_SRE_FAST)
  59 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  60
  61 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  62
  63 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
  64         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  65         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  66
  67 #define I2C_PMIC        1
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size = imx_ddr_size();
  72
  73         return 0;
  74 }
  75
  76 static iomux_v3_cfg_t const uart4_pads[] = {
  77         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  78         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  79 };
  80
  81
  82 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
  83 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
  84         .scl = {
  85                 .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
  86                 .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
  87                 .gp = IMX_GPIO_NR(2, 30)
  88         },
  89         .sda = {
  90                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  91                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  92                 .gp = IMX_GPIO_NR(4, 13)
  93         }
  94 };
  95
  96 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  97         .scl = {
  98                 .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
  99                 .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
 100                 .gp = IMX_GPIO_NR(2, 30)
 101         },
 102         .sda = {
 103                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 104                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 105                 .gp = IMX_GPIO_NR(4, 13)
 106         }
 107 };
 108
 109 #ifndef CONFIG_SYS_FLASH_CFI
 110 /*
 111  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
 112  * Compass Sensor, Accelerometer, Res Touch
 113  */
 114 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
 115         .scl = {
 116                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 117                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 118                 .gp = IMX_GPIO_NR(1, 3)
 119         },
 120         .sda = {
 121                 .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
 122                 .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
 123                 .gp = IMX_GPIO_NR(3, 18)
 124         }
 125 };
 126
 127 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 128         .scl = {
 129                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 130                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 131                 .gp = IMX_GPIO_NR(1, 3)
 132         },
 133         .sda = {
 134                 .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
 135                 .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
 136                 .gp = IMX_GPIO_NR(3, 18)
 137         }
 138 };
 139 #endif
 140
 141 static iomux_v3_cfg_t const i2c3_pads[] = {
 142         IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 143 };
 144
 145 static iomux_v3_cfg_t const port_exp[] = {
 146         IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 147 };
 148
 149 #ifdef CONFIG_MTD_NOR_FLASH
 150 static iomux_v3_cfg_t const eimnor_pads[] = {
 151         IOMUX_PADS(PAD_EIM_D16__EIM_DATA16      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 152         IOMUX_PADS(PAD_EIM_D17__EIM_DATA17      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 153         IOMUX_PADS(PAD_EIM_D18__EIM_DATA18      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 154         IOMUX_PADS(PAD_EIM_D19__EIM_DATA19      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 155         IOMUX_PADS(PAD_EIM_D20__EIM_DATA20      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 156         IOMUX_PADS(PAD_EIM_D21__EIM_DATA21      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 157         IOMUX_PADS(PAD_EIM_D22__EIM_DATA22      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 158         IOMUX_PADS(PAD_EIM_D23__EIM_DATA23      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 159         IOMUX_PADS(PAD_EIM_D24__EIM_DATA24      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 160         IOMUX_PADS(PAD_EIM_D25__EIM_DATA25      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 161         IOMUX_PADS(PAD_EIM_D26__EIM_DATA26      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 162         IOMUX_PADS(PAD_EIM_D27__EIM_DATA27      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 163         IOMUX_PADS(PAD_EIM_D28__EIM_DATA28      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 164         IOMUX_PADS(PAD_EIM_D29__EIM_DATA29      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 165         IOMUX_PADS(PAD_EIM_D30__EIM_DATA30      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 166         IOMUX_PADS(PAD_EIM_D31__EIM_DATA31      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 167         IOMUX_PADS(PAD_EIM_DA0__EIM_AD00        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 168         IOMUX_PADS(PAD_EIM_DA1__EIM_AD01        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 169         IOMUX_PADS(PAD_EIM_DA2__EIM_AD02        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 170         IOMUX_PADS(PAD_EIM_DA3__EIM_AD03        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 171         IOMUX_PADS(PAD_EIM_DA4__EIM_AD04        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 172         IOMUX_PADS(PAD_EIM_DA5__EIM_AD05        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 173         IOMUX_PADS(PAD_EIM_DA6__EIM_AD06        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 174         IOMUX_PADS(PAD_EIM_DA7__EIM_AD07        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 175         IOMUX_PADS(PAD_EIM_DA8__EIM_AD08        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 176         IOMUX_PADS(PAD_EIM_DA9__EIM_AD09        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 177         IOMUX_PADS(PAD_EIM_DA10__EIM_AD10       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 178         IOMUX_PADS(PAD_EIM_DA11__EIM_AD11       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 179         IOMUX_PADS(PAD_EIM_DA12__EIM_AD12       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 180         IOMUX_PADS(PAD_EIM_DA13__EIM_AD13       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 181         IOMUX_PADS(PAD_EIM_DA14__EIM_AD14       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 182         IOMUX_PADS(PAD_EIM_DA15__EIM_AD15       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 183         IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 184         IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 185         IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 186         IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 187         IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 188         IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 189         IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 190         IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23      | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
 191         IOMUX_PADS(PAD_EIM_OE__EIM_OE_B         | MUX_PAD_CTRL(NO_PAD_CTRL)),
 192         IOMUX_PADS(PAD_EIM_RW__EIM_RW           | MUX_PAD_CTRL(NO_PAD_CTRL)),
 193         IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B       | MUX_PAD_CTRL(NO_PAD_CTRL)),
 194 };
 195
 196 static void eimnor_cs_setup(void)
 197 {
 198         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 199
 200         writel(0x00020181, &weim_regs->cs0gcr1);
 201         writel(0x00000001, &weim_regs->cs0gcr2);
 202         writel(0x0a020000, &weim_regs->cs0rcr1);
 203         writel(0x0000c000, &weim_regs->cs0rcr2);
 204         writel(0x0804a240, &weim_regs->cs0wcr1);
 205         writel(0x00000120, &weim_regs->wcr);
 206
 207         set_chipselect_size(CS0_128);
 208 }
 209
 210 static void eim_clk_setup(void)
 211 {
 212         struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 213         int cscmr1, ccgr6;
 214
 215
 216         /* Turn off EIM clock */
 217         ccgr6 = readl(&imx_ccm->CCGR6);
 218         ccgr6 &= ~(0x3 << 10);
 219         writel(ccgr6, &imx_ccm->CCGR6);
 220
 221         /*
 222          * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
 223          * and aclk_eim_slow_podf = 01 --> divide by 2
 224          * so that we can have EIM at the maximum clock of 132MHz
 225          */
 226         cscmr1 = readl(&imx_ccm->cscmr1);
 227         cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
 228                     MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
 229         cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
 230         writel(cscmr1, &imx_ccm->cscmr1);
 231
 232         /* Turn on EIM clock */
 233         ccgr6 |= (0x3 << 10);
 234         writel(ccgr6, &imx_ccm->CCGR6);
 235 }
 236
 237 static void setup_iomux_eimnor(void)
 238 {
 239         SETUP_IOMUX_PADS(eimnor_pads);
 240
 241         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 242
 243         eimnor_cs_setup();
 244 }
 245 #endif
 246
 247
 248 static iomux_v3_cfg_t const usdhc3_pads[] = {
 249         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 250         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD         | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 251         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 252         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 253         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 254         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 255         IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 256         IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 257         IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 258         IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7      | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 259         IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT     | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 260         IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 261 };
 262
 263 static void setup_iomux_uart(void)
 264 {
 265         SETUP_IOMUX_PADS(uart4_pads);
 266 }
 267
 268 #ifdef CONFIG_FSL_ESDHC_IMX
 269 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 270         {USDHC3_BASE_ADDR},
 271 };
 272
 273 int board_mmc_getcd(struct mmc *mmc)
 274 {
 275         gpio_direction_input(IMX_GPIO_NR(6, 15));
 276         return !gpio_get_value(IMX_GPIO_NR(6, 15));
 277 }
 278
 279 int board_mmc_init(struct bd_info *bis)
 280 {
 281         SETUP_IOMUX_PADS(usdhc3_pads);
 282
 283         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 284         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 285 }
 286 #endif
 287
 288 #ifdef CONFIG_NAND_MXS
 289 static iomux_v3_cfg_t gpmi_pads[] = {
 290         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE      | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 291         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE      | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 292         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 293         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B  | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
 294         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 295         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B       | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 296         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B       | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 297         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 298         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 299         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 300         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 301         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 302         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 303         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 304         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
 305         IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS       | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
 306 };
 307
 308 static void setup_gpmi_nand(void)
 309 {
 310         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 311
 312         /* config gpmi nand iomux */
 313         SETUP_IOMUX_PADS(gpmi_pads);
 314
 315         setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 316                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 317                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
 318
 319         /* enable apbh clock gating */
 320         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 321 }
 322 #endif
 323
 324 #ifdef CONFIG_REVISION_TAG
 325 u32 get_board_rev(void)
 326 {
 327         int rev = nxp_board_rev();
 328
 329         return (get_cpu_rev() & ~(0xF << 8)) | rev;
 330 }
 331 #endif
 332
 333 static int ar8031_phy_fixup(struct phy_device *phydev)
 334 {
 335         unsigned short val;
 336
 337         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 338         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 339         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 340         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 341
 342         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 343         val &= 0xffe3;
 344         val |= 0x18;
 345         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 346
 347         /* introduce tx clock delay */
 348         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 349         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 350         val |= 0x0100;
 351         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 352
 353         return 0;
 354 }
 355
 356 int board_phy_config(struct phy_device *phydev)
 357 {
 358         ar8031_phy_fixup(phydev);
 359
 360         if (phydev->drv->config)
 361                 phydev->drv->config(phydev);
 362
 363         return 0;
 364 }
 365
 366 #if defined(CONFIG_VIDEO_IPUV3)
 367 static void disable_lvds(struct display_info_t const *dev)
 368 {
 369         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 370
 371         clrbits_le32(&iomux->gpr[2],
 372                      IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 373                      IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 374 }
 375
 376 static void do_enable_hdmi(struct display_info_t const *dev)
 377 {
 378         disable_lvds(dev);
 379         imx_enable_hdmi_phy();
 380 }
 381
 382 struct display_info_t const displays[] = {{
 383         .bus    = -1,
 384         .addr   = 0,
 385         .pixfmt = IPU_PIX_FMT_RGB666,
 386         .detect = NULL,
 387         .enable = NULL,
 388         .mode   = {
 389                 .name           = "Hannstar-XGA",
 390                 .refresh        = 60,
 391                 .xres           = 1024,
 392                 .yres           = 768,
 393                 .pixclock       = 15385,
 394                 .left_margin    = 220,
 395                 .right_margin   = 40,
 396                 .upper_margin   = 21,
 397                 .lower_margin   = 7,
 398                 .hsync_len      = 60,
 399                 .vsync_len      = 10,
 400                 .sync           = FB_SYNC_EXT,
 401                 .vmode          = FB_VMODE_NONINTERLACED
 402 } }, {
 403         .bus    = -1,
 404         .addr   = 0,
 405         .pixfmt = IPU_PIX_FMT_RGB24,
 406         .detect = detect_hdmi,
 407         .enable = do_enable_hdmi,
 408         .mode   = {
 409                 .name           = "HDMI",
 410                 .refresh        = 60,
 411                 .xres           = 1024,
 412                 .yres           = 768,
 413                 .pixclock       = 15385,
 414                 .left_margin    = 220,
 415                 .right_margin   = 40,
 416                 .upper_margin   = 21,
 417                 .lower_margin   = 7,
 418                 .hsync_len      = 60,
 419                 .vsync_len      = 10,
 420                 .sync           = FB_SYNC_EXT,
 421                 .vmode          = FB_VMODE_NONINTERLACED,
 422 } } };
 423 size_t display_count = ARRAY_SIZE(displays);
 424
 425 iomux_v3_cfg_t const backlight_pads[] = {
 426         IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 427 };
 428
 429 static void setup_iomux_backlight(void)
 430 {
 431         gpio_request(IMX_GPIO_NR(2, 9), "backlight");
 432         gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
 433         SETUP_IOMUX_PADS(backlight_pads);
 434 }
 435
 436 static void setup_display(void)
 437 {
 438         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 439         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 440         int reg;
 441
 442         setup_iomux_backlight();
 443         enable_ipu_clock();
 444         imx_setup_hdmi();
 445
 446         /* Turn on LDB_DI0 and LDB_DI1 clocks */
 447         reg = readl(&mxc_ccm->CCGR3);
 448         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 449         writel(reg, &mxc_ccm->CCGR3);
 450
 451         /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
 452         reg = readl(&mxc_ccm->cs2cdr);
 453         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
 454                  MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 455         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
 456                (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 457         writel(reg, &mxc_ccm->cs2cdr);
 458
 459         reg = readl(&mxc_ccm->cscmr2);
 460         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 461         writel(reg, &mxc_ccm->cscmr2);
 462
 463         reg = readl(&mxc_ccm->chsccdr);
 464         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 465                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 466         reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
 467                 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 468         writel(reg, &mxc_ccm->chsccdr);
 469
 470         reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
 471               IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 472               IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 473               IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
 474               IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 475               IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
 476               IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 477               IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
 478         writel(reg, &iomux->gpr[2]);
 479
 480         reg = readl(&iomux->gpr[3]);
 481         reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 482                  IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
 483         reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 484                 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
 485                (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 486                 IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
 487         writel(reg, &iomux->gpr[3]);
 488 }
 489 #endif /* CONFIG_VIDEO_IPUV3 */
 490
 491 /*
 492  * Do not overwrite the console
 493  * Use always serial for U-Boot console
 494  */
 495 int overwrite_console(void)
 496 {
 497         return 1;
 498 }
 499
 500 int board_early_init_f(void)
 501 {
 502         setup_iomux_uart();
 503
 504 #ifdef CONFIG_NAND_MXS
 505         setup_gpmi_nand();
 506 #endif
 507
 508 #ifdef CONFIG_MTD_NOR_FLASH
 509         eim_clk_setup();
 510 #endif
 511         return 0;
 512 }
 513
 514 int board_init(void)
 515 {
 516         /* address of boot parameters */
 517         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 518
 519         /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
 520         if (is_mx6dq() || is_mx6dqp())
 521                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
 522         else
 523                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 524         /* I2C 3 Steer */
 525         gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
 526         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 527         SETUP_IOMUX_PADS(i2c3_pads);
 528 #ifndef CONFIG_SYS_FLASH_CFI
 529         if (is_mx6dq() || is_mx6dqp())
 530                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
 531         else
 532                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
 533 #endif
 534         gpio_request(IMX_GPIO_NR(1, 15), "expander en");
 535         gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
 536         SETUP_IOMUX_PADS(port_exp);
 537
 538 #ifdef CONFIG_VIDEO_IPUV3
 539         setup_display();
 540 #endif
 541
 542 #ifdef CONFIG_MTD_NOR_FLASH
 543         setup_iomux_eimnor();
 544 #endif
 545         return 0;
 546 }
 547
 548 #ifdef CONFIG_MXC_SPI
 549 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 550 {
 551         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
 552 }
 553 #endif
 554
 555 int power_init_board(void)
 556 {
 557         struct pmic *p;
 558         unsigned int value;
 559
 560         p = pfuze_common_init(I2C_PMIC);
 561         if (!p)
 562                 return -ENODEV;
 563
 564         if (is_mx6dqp()) {
 565                 /* set SW2 staby volatage 0.975V*/
 566                 pmic_reg_read(p, PFUZE100_SW2STBY, &value);
 567                 value &= ~0x3f;
 568                 value |= 0x17;
 569                 pmic_reg_write(p, PFUZE100_SW2STBY, value);
 570         }
 571
 572         return pfuze_mode_init(p, APS_PFM);
 573 }
 574
 575 #ifdef CONFIG_CMD_BMODE
 576 static const struct boot_mode board_boot_modes[] = {
 577         /* 4 bit bus width */
 578         {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 579         {NULL,   0},
 580 };
 581 #endif
 582
 583 int board_late_init(void)
 584 {
 585 #ifdef CONFIG_CMD_BMODE
 586         add_board_boot_modes(board_boot_modes);
 587 #endif
 588
 589 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 590         env_set("board_name", "SABREAUTO");
 591
 592         if (is_mx6dqp())
 593                 env_set("board_rev", "MX6QP");
 594         else if (is_mx6dq())
 595                 env_set("board_rev", "MX6Q");
 596         else if (is_mx6sdl())
 597                 env_set("board_rev", "MX6DL");
 598 #endif
 599
 600         return 0;
 601 }
 602
 603 int checkboard(void)
 604 {
 605         printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
 606
 607         return 0;
 608 }
 609
 610 #ifdef CONFIG_USB_EHCI_MX6
 611 int board_ehci_hcd_init(int port)
 612 {
 613         switch (port) {
 614         case 0:
 615                 /*
 616                   * Set daisy chain for otg_pin_id on 6q.
 617                  *  For 6dl, this bit is reserved.
 618                  */
 619                 imx_iomux_set_gpr_register(1, 13, 1, 0);
 620                 break;
 621         case 1:
 622                 break;
 623         default:
 624                 printf("MXC USB port %d not yet supported\n", port);
 625                 return -EINVAL;
 626         }
 627         return 0;
 628 }
 629 #endif
 630
 631 #ifdef CONFIG_SPL_BUILD
 632 #include <asm/arch/mx6-ddr.h>
 633 #include <spl.h>
 634 #include <linux/libfdt.h>
 635
 636 #ifdef CONFIG_SPL_OS_BOOT
 637 int spl_start_uboot(void)
 638 {
 639         return 0;
 640 }
 641 #endif
 642
 643 static void ccgr_init(void)
 644 {
 645         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 646
 647         writel(0x00C03F3F, &ccm->CCGR0);
 648         writel(0x0030FC03, &ccm->CCGR1);
 649         writel(0x0FFFC000, &ccm->CCGR2);
 650         writel(0x3FF00000, &ccm->CCGR3);
 651         writel(0x00FFF300, &ccm->CCGR4);
 652         writel(0x0F0000C3, &ccm->CCGR5);
 653         writel(0x000003FF, &ccm->CCGR6);
 654 }
 655
 656 static int mx6q_dcd_table[] = {
 657         0x020e0798, 0x000C0000,
 658         0x020e0758, 0x00000000,
 659         0x020e0588, 0x00000030,
 660         0x020e0594, 0x00000030,
 661         0x020e056c, 0x00000030,
 662         0x020e0578, 0x00000030,
 663         0x020e074c, 0x00000030,
 664         0x020e057c, 0x00000030,
 665         0x020e058c, 0x00000000,
 666         0x020e059c, 0x00000030,
 667         0x020e05a0, 0x00000030,
 668         0x020e078c, 0x00000030,
 669         0x020e0750, 0x00020000,
 670         0x020e05a8, 0x00000028,
 671         0x020e05b0, 0x00000028,
 672         0x020e0524, 0x00000028,
 673         0x020e051c, 0x00000028,
 674         0x020e0518, 0x00000028,
 675         0x020e050c, 0x00000028,
 676         0x020e05b8, 0x00000028,
 677         0x020e05c0, 0x00000028,
 678         0x020e0774, 0x00020000,
 679         0x020e0784, 0x00000028,
 680         0x020e0788, 0x00000028,
 681         0x020e0794, 0x00000028,
 682         0x020e079c, 0x00000028,
 683         0x020e07a0, 0x00000028,
 684         0x020e07a4, 0x00000028,
 685         0x020e07a8, 0x00000028,
 686         0x020e0748, 0x00000028,
 687         0x020e05ac, 0x00000028,
 688         0x020e05b4, 0x00000028,
 689         0x020e0528, 0x00000028,
 690         0x020e0520, 0x00000028,
 691         0x020e0514, 0x00000028,
 692         0x020e0510, 0x00000028,
 693         0x020e05bc, 0x00000028,
 694         0x020e05c4, 0x00000028,
 695         0x021b0800, 0xa1390003,
 696         0x021b080c, 0x001F001F,
 697         0x021b0810, 0x001F001F,
 698         0x021b480c, 0x001F001F,
 699         0x021b4810, 0x001F001F,
 700         0x021b083c, 0x43260335,
 701         0x021b0840, 0x031A030B,
 702         0x021b483c, 0x4323033B,
 703         0x021b4840, 0x0323026F,
 704         0x021b0848, 0x483D4545,
 705         0x021b4848, 0x44433E48,
 706         0x021b0850, 0x41444840,
 707         0x021b4850, 0x4835483E,
 708         0x021b081c, 0x33333333,
 709         0x021b0820, 0x33333333,
 710         0x021b0824, 0x33333333,
 711         0x021b0828, 0x33333333,
 712         0x021b481c, 0x33333333,
 713         0x021b4820, 0x33333333,
 714         0x021b4824, 0x33333333,
 715         0x021b4828, 0x33333333,
 716         0x021b08b8, 0x00000800,
 717         0x021b48b8, 0x00000800,
 718         0x021b0004, 0x00020036,
 719         0x021b0008, 0x09444040,
 720         0x021b000c, 0x8A8F7955,
 721         0x021b0010, 0xFF328F64,
 722         0x021b0014, 0x01FF00DB,
 723         0x021b0018, 0x00001740,
 724         0x021b001c, 0x00008000,
 725         0x021b002c, 0x000026d2,
 726         0x021b0030, 0x008F1023,
 727         0x021b0040, 0x00000047,
 728         0x021b0000, 0x841A0000,
 729         0x021b001c, 0x04088032,
 730         0x021b001c, 0x00008033,
 731         0x021b001c, 0x00048031,
 732         0x021b001c, 0x09408030,
 733         0x021b001c, 0x04008040,
 734         0x021b0020, 0x00005800,
 735         0x021b0818, 0x00011117,
 736         0x021b4818, 0x00011117,
 737         0x021b0004, 0x00025576,
 738         0x021b0404, 0x00011006,
 739         0x021b001c, 0x00000000,
 740         0x020c4068, 0x00C03F3F,
 741         0x020c406c, 0x0030FC03,
 742         0x020c4070, 0x0FFFC000,
 743         0x020c4074, 0x3FF00000,
 744         0x020c4078, 0xFFFFF300,
 745         0x020c407c, 0x0F0000F3,
 746         0x020c4080, 0x00000FFF,
 747         0x020e0010, 0xF00000CF,
 748         0x020e0018, 0x007F007F,
 749         0x020e001c, 0x007F007F,
 750 };
 751
 752 static int mx6qp_dcd_table[] = {
 753         0x020e0798, 0x000C0000,
 754         0x020e0758, 0x00000000,
 755         0x020e0588, 0x00000030,
 756         0x020e0594, 0x00000030,
 757         0x020e056c, 0x00000030,
 758         0x020e0578, 0x00000030,
 759         0x020e074c, 0x00000030,
 760         0x020e057c, 0x00000030,
 761         0x020e058c, 0x00000000,
 762         0x020e059c, 0x00000030,
 763         0x020e05a0, 0x00000030,
 764         0x020e078c, 0x00000030,
 765         0x020e0750, 0x00020000,
 766         0x020e05a8, 0x00000030,
 767         0x020e05b0, 0x00000030,
 768         0x020e0524, 0x00000030,
 769         0x020e051c, 0x00000030,
 770         0x020e0518, 0x00000030,
 771         0x020e050c, 0x00000030,
 772         0x020e05b8, 0x00000030,
 773         0x020e05c0, 0x00000030,
 774         0x020e0774, 0x00020000,
 775         0x020e0784, 0x00000030,
 776         0x020e0788, 0x00000030,
 777         0x020e0794, 0x00000030,
 778         0x020e079c, 0x00000030,
 779         0x020e07a0, 0x00000030,
 780         0x020e07a4, 0x00000030,
 781         0x020e07a8, 0x00000030,
 782         0x020e0748, 0x00000030,
 783         0x020e05ac, 0x00000030,
 784         0x020e05b4, 0x00000030,
 785         0x020e0528, 0x00000030,
 786         0x020e0520, 0x00000030,
 787         0x020e0514, 0x00000030,
 788         0x020e0510, 0x00000030,
 789         0x020e05bc, 0x00000030,
 790         0x020e05c4, 0x00000030,
 791         0x021b0800, 0xa1390003,
 792         0x021b080c, 0x001b001e,
 793         0x021b0810, 0x002e0029,
 794         0x021b480c, 0x001b002a,
 795         0x021b4810, 0x0019002c,
 796         0x021b083c, 0x43240334,
 797         0x021b0840, 0x0324031a,
 798         0x021b483c, 0x43340344,
 799         0x021b4840, 0x03280276,
 800         0x021b0848, 0x44383A3E,
 801         0x021b4848, 0x3C3C3846,
 802         0x021b0850, 0x2e303230,
 803         0x021b4850, 0x38283E34,
 804         0x021b081c, 0x33333333,
 805         0x021b0820, 0x33333333,
 806         0x021b0824, 0x33333333,
 807         0x021b0828, 0x33333333,
 808         0x021b481c, 0x33333333,
 809         0x021b4820, 0x33333333,
 810         0x021b4824, 0x33333333,
 811         0x021b4828, 0x33333333,
 812         0x021b08c0, 0x24912492,
 813         0x021b48c0, 0x24912492,
 814         0x021b08b8, 0x00000800,
 815         0x021b48b8, 0x00000800,
 816         0x021b0004, 0x00020036,
 817         0x021b0008, 0x09444040,
 818         0x021b000c, 0x898E7955,
 819         0x021b0010, 0xFF328F64,
 820         0x021b0014, 0x01FF00DB,
 821         0x021b0018, 0x00001740,
 822         0x021b001c, 0x00008000,
 823         0x021b002c, 0x000026d2,
 824         0x021b0030, 0x008E1023,
 825         0x021b0040, 0x00000047,
 826         0x021b0400, 0x14420000,
 827         0x021b0000, 0x841A0000,
 828         0x00bb0008, 0x00000004,
 829         0x00bb000c, 0x2891E41A,
 830         0x00bb0038, 0x00000564,
 831         0x00bb0014, 0x00000040,
 832         0x00bb0028, 0x00000020,
 833         0x00bb002c, 0x00000020,
 834         0x021b001c, 0x04088032,
 835         0x021b001c, 0x00008033,
 836         0x021b001c, 0x00048031,
 837         0x021b001c, 0x09408030,
 838         0x021b001c, 0x04008040,
 839         0x021b0020, 0x00005800,
 840         0x021b0818, 0x00011117,
 841         0x021b4818, 0x00011117,
 842         0x021b0004, 0x00025576,
 843         0x021b0404, 0x00011006,
 844         0x021b001c, 0x00000000,
 845         0x020c4068, 0x00C03F3F,
 846         0x020c406c, 0x0030FC03,
 847         0x020c4070, 0x0FFFC000,
 848         0x020c4074, 0x3FF00000,
 849         0x020c4078, 0xFFFFF300,
 850         0x020c407c, 0x0F0000F3,
 851         0x020c4080, 0x00000FFF,
 852         0x020e0010, 0xF00000CF,
 853         0x020e0018, 0x77177717,
 854         0x020e001c, 0x77177717,
 855 };
 856
 857 static int mx6dl_dcd_table[] = {
 858         0x020e0774, 0x000C0000,
 859         0x020e0754, 0x00000000,
 860         0x020e04ac, 0x00000030,
 861         0x020e04b0, 0x00000030,
 862         0x020e0464, 0x00000030,
 863         0x020e0490, 0x00000030,
 864         0x020e074c, 0x00000030,
 865         0x020e0494, 0x00000030,
 866         0x020e04a0, 0x00000000,
 867         0x020e04b4, 0x00000030,
 868         0x020e04b8, 0x00000030,
 869         0x020e076c, 0x00000030,
 870         0x020e0750, 0x00020000,
 871         0x020e04bc, 0x00000028,
 872         0x020e04c0, 0x00000028,
 873         0x020e04c4, 0x00000028,
 874         0x020e04c8, 0x00000028,
 875         0x020e04cc, 0x00000028,
 876         0x020e04d0, 0x00000028,
 877         0x020e04d4, 0x00000028,
 878         0x020e04d8, 0x00000028,
 879         0x020e0760, 0x00020000,
 880         0x020e0764, 0x00000028,
 881         0x020e0770, 0x00000028,
 882         0x020e0778, 0x00000028,
 883         0x020e077c, 0x00000028,
 884         0x020e0780, 0x00000028,
 885         0x020e0784, 0x00000028,
 886         0x020e078c, 0x00000028,
 887         0x020e0748, 0x00000028,
 888         0x020e0470, 0x00000028,
 889         0x020e0474, 0x00000028,
 890         0x020e0478, 0x00000028,
 891         0x020e047c, 0x00000028,
 892         0x020e0480, 0x00000028,
 893         0x020e0484, 0x00000028,
 894         0x020e0488, 0x00000028,
 895         0x020e048c, 0x00000028,
 896         0x021b0800, 0xa1390003,
 897         0x021b080c, 0x001F001F,
 898         0x021b0810, 0x001F001F,
 899         0x021b480c, 0x001F001F,
 900         0x021b4810, 0x001F001F,
 901         0x021b083c, 0x42190217,
 902         0x021b0840, 0x017B017B,
 903         0x021b483c, 0x4176017B,
 904         0x021b4840, 0x015F016C,
 905         0x021b0848, 0x4C4C4D4C,
 906         0x021b4848, 0x4A4D4C48,
 907         0x021b0850, 0x3F3F3F40,
 908         0x021b4850, 0x3538382E,
 909         0x021b081c, 0x33333333,
 910         0x021b0820, 0x33333333,
 911         0x021b0824, 0x33333333,
 912         0x021b0828, 0x33333333,
 913         0x021b481c, 0x33333333,
 914         0x021b4820, 0x33333333,
 915         0x021b4824, 0x33333333,
 916         0x021b4828, 0x33333333,
 917         0x021b08b8, 0x00000800,
 918         0x021b48b8, 0x00000800,
 919         0x021b0004, 0x00020025,
 920         0x021b0008, 0x00333030,
 921         0x021b000c, 0x676B5313,
 922         0x021b0010, 0xB66E8B63,
 923         0x021b0014, 0x01FF00DB,
 924         0x021b0018, 0x00001740,
 925         0x021b001c, 0x00008000,
 926         0x021b002c, 0x000026d2,
 927         0x021b0030, 0x006B1023,
 928         0x021b0040, 0x00000047,
 929         0x021b0000, 0x841A0000,
 930         0x021b001c, 0x04008032,
 931         0x021b001c, 0x00008033,
 932         0x021b001c, 0x00048031,
 933         0x021b001c, 0x05208030,
 934         0x021b001c, 0x04008040,
 935         0x021b0020, 0x00005800,
 936         0x021b0818, 0x00011117,
 937         0x021b4818, 0x00011117,
 938         0x021b0004, 0x00025565,
 939         0x021b0404, 0x00011006,
 940         0x021b001c, 0x00000000,
 941         0x020c4068, 0x00C03F3F,
 942         0x020c406c, 0x0030FC03,
 943         0x020c4070, 0x0FFFC000,
 944         0x020c4074, 0x3FF00000,
 945         0x020c4078, 0xFFFFF300,
 946         0x020c407c, 0x0F0000C3,
 947         0x020c4080, 0x00000FFF,
 948         0x020e0010, 0xF00000CF,
 949         0x020e0018, 0x007F007F,
 950         0x020e001c, 0x007F007F,
 951 };
 952
 953 static void ddr_init(int *table, int size)
 954 {
 955         int i;
 956
 957         for (i = 0; i < size / 2 ; i++)
 958                 writel(table[2 * i + 1], table[2 * i]);
 959 }
 960
 961 static void spl_dram_init(void)
 962 {
 963         if (is_mx6dq())
 964                 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
 965         else if (is_mx6dqp())
 966                 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
 967         else if (is_mx6sdl())
 968                 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
 969 }
 970
 971 void board_init_f(ulong dummy)
 972 {
 973         /* DDR initialization */
 974         spl_dram_init();
 975
 976         /* setup AIPS and disable watchdog */
 977         arch_cpu_init();
 978
 979         ccgr_init();
 980         gpr_init();
 981
 982         /* iomux and setup of i2c */
 983         board_early_init_f();
 984
 985         /* setup GP timer */
 986         timer_init();
 987
 988         /* UART clocks enabled and gd valid - init serial console */
 989         preloader_console_init();
 990
 991         /* Clear the BSS. */
 992         memset(__bss_start, 0, __bss_end - __bss_start);
 993
 994         /* load/boot image from boot device */
 995         board_init_r(NULL, 0);
 996 }
 997 #endif
 998
 999 #ifdef CONFIG_SPL_LOAD_FIT
1000 int board_fit_config_name_match(const char *name)
1001 {
1002         if (is_mx6dq()) {
1003                 if (!strcmp(name, "imx6q-sabreauto"))
1004                         return 0;
1005         } else if (is_mx6dqp()) {
1006                 if (!strcmp(name, "imx6qp-sabreauto"))
1007                         return 0;
1008         } else if (is_mx6dl()) {
1009                 if (!strcmp(name, "imx6dl-sabreauto"))
1010                         return 0;
1011         }
1012
1013         return -1;
1014 }
1015 #endif