board/freescale/mx51evk/mx51evk.c

   1 /*
   2  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/gpio.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/mx5x_pins.h>
  28 #include <asm/arch/iomux.h>
  29 #include <asm/errno.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <asm/arch/crm_regs.h>
  32 #include <asm/arch/clock.h>
  33 #include <i2c.h>
  34 #include <mmc.h>
  35 #include <fsl_esdhc.h>
  36 #include <pmic.h>
  37 #include <fsl_pmic.h>
  38 #include <mc13892.h>
  39 #include <usb/ehci-fsl.h>
  40 #include <linux/fb.h>
  41 #include <ipu_pixfmt.h>
  42
  43 #define MX51EVK_LCD_3V3         IMX_GPIO_NR(4, 9)
  44 #define MX51EVK_LCD_5V          IMX_GPIO_NR(4, 10)
  45 #define MX51EVK_LCD_BACKLIGHT   IMX_GPIO_NR(3, 4)
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 #ifdef CONFIG_FSL_ESDHC
  50 struct fsl_esdhc_cfg esdhc_cfg[2] = {
  51         {MMC_SDHC1_BASE_ADDR},
  52         {MMC_SDHC2_BASE_ADDR},
  53 };
  54 #endif
  55
  56 int dram_init(void)
  57 {
  58         /* dram_init must store complete ramsize in gd->ram_size */
  59         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  60                                 PHYS_SDRAM_1_SIZE);
  61         return 0;
  62 }
  63
  64 u32 get_board_rev(void)
  65 {
  66         u32 rev = get_cpu_rev();
  67         if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
  68                 rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
  69         return rev;
  70 }
  71
  72 static void setup_iomux_uart(void)
  73 {
  74         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
  75                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
  76
  77         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
  78         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
  79         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
  80         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
  81         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
  82         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
  83         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
  84         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
  85 }
  86
  87 static void setup_iomux_fec(void)
  88 {
  89         /*FEC_MDIO*/
  90         mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
  91         mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
  92
  93         /*FEC_MDC*/
  94         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
  95         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
  96
  97         /* FEC RDATA[3] */
  98         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
  99         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
 100
 101         /* FEC RDATA[2] */
 102         mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
 103         mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
 104
 105         /* FEC RDATA[1] */
 106         mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
 107         mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
 108
 109         /* FEC RDATA[0] */
 110         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
 111         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
 112
 113         /* FEC TDATA[3] */
 114         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
 115         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
 116
 117         /* FEC TDATA[2] */
 118         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
 119         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
 120
 121         /* FEC TDATA[1] */
 122         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
 123         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
 124
 125         /* FEC TDATA[0] */
 126         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
 127         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
 128
 129         /* FEC TX_EN */
 130         mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
 131         mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
 132
 133         /* FEC TX_ER */
 134         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
 135         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
 136
 137         /* FEC TX_CLK */
 138         mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
 139         mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
 140
 141         /* FEC TX_COL */
 142         mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
 143         mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
 144
 145         /* FEC RX_CLK */
 146         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
 147         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
 148
 149         /* FEC RX_CRS */
 150         mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
 151         mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
 152
 153         /* FEC RX_ER */
 154         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
 155         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
 156
 157         /* FEC RX_DV */
 158         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
 159         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
 160 }
 161
 162 #ifdef CONFIG_MXC_SPI
 163 static void setup_iomux_spi(void)
 164 {
 165         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 166         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 167         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
 168
 169         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 170         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 171         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
 172
 173         /* de-select SS1 of instance: ecspi1. */
 174         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
 175         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
 176
 177         /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
 178         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
 179         mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
 180
 181         /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
 182         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
 183         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
 184
 185         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 186         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 187         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
 188 }
 189 #endif
 190
 191 #ifdef CONFIG_USB_EHCI_MX5
 192 #define MX51EVK_USBH1_HUB_RST   IOMUX_TO_GPIO(MX51_PIN_GPIO1_7) /* GPIO1_7 */
 193 #define MX51EVK_USBH1_STP       IOMUX_TO_GPIO(MX51_PIN_USBH1_STP) /* GPIO1_27 */
 194 #define MX51EVK_USB_CLK_EN_B    IOMUX_TO_GPIO(MX51_PIN_EIM_D18) /* GPIO2_1 */
 195 #define MX51EVK_USB_PHY_RESET   IOMUX_TO_GPIO(MX51_PIN_EIM_D21) /* GPIO2_5 */
 196
 197 #define USBH1_PAD       (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |          \
 198                          PAD_CTL_100K_PU | PAD_CTL_PUE_PULL |           \
 199                          PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE)
 200 #define GPIO_PAD        (PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE |        \
 201                          PAD_CTL_SRE_FAST)
 202 #define NO_PAD          (1 << 16)
 203
 204 static void setup_usb_h1(void)
 205 {
 206         setup_iomux_usb_h1();
 207
 208         /* GPIO_1_7 for USBH1 hub reset */
 209         mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
 210         mxc_iomux_set_pad(MX51_PIN_GPIO1_7, NO_PAD);
 211
 212         /* GPIO_2_1 */
 213         mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
 214         mxc_iomux_set_pad(MX51_PIN_EIM_D17, GPIO_PAD);
 215
 216         /* GPIO_2_5 for USB PHY reset */
 217         mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
 218         mxc_iomux_set_pad(MX51_PIN_EIM_D21, GPIO_PAD);
 219 }
 220
 221 int board_ehci_hcd_init(int port)
 222 {
 223         /* Set USBH1_STP to GPIO and toggle it */
 224         mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
 225         mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
 226
 227         gpio_direction_output(MX51EVK_USBH1_STP, 0);
 228         gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
 229         mdelay(10);
 230         gpio_set_value(MX51EVK_USBH1_STP, 1);
 231
 232         /* Set back USBH1_STP to be function */
 233         mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
 234         mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USBH1_PAD);
 235
 236         /* De-assert USB PHY RESETB */
 237         gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
 238
 239         /* Drive USB_CLK_EN_B line low */
 240         gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
 241
 242         /* Reset USB hub */
 243         gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
 244         mdelay(2);
 245         gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
 246         return 0;
 247 }
 248 #endif
 249
 250 static void power_init(void)
 251 {
 252         unsigned int val;
 253         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 254         struct pmic *p;
 255
 256         pmic_init();
 257         p = get_pmic();
 258
 259         /* Write needed to Power Gate 2 register */
 260         pmic_reg_read(p, REG_POWER_MISC, &val);
 261         val &= ~PWGT2SPIEN;
 262         pmic_reg_write(p, REG_POWER_MISC, val);
 263
 264         /* Externally powered */
 265         pmic_reg_read(p, REG_CHARGE, &val);
 266         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
 267         pmic_reg_write(p, REG_CHARGE, val);
 268
 269         /* power up the system first */
 270         pmic_reg_write(p, REG_POWER_MISC, PWUP);
 271
 272         /* Set core voltage to 1.1V */
 273         pmic_reg_read(p, REG_SW_0, &val);
 274         val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
 275         pmic_reg_write(p, REG_SW_0, val);
 276
 277         /* Setup VCC (SW2) to 1.25 */
 278         pmic_reg_read(p, REG_SW_1, &val);
 279         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 280         pmic_reg_write(p, REG_SW_1, val);
 281
 282         /* Setup 1V2_DIG1 (SW3) to 1.25 */
 283         pmic_reg_read(p, REG_SW_2, &val);
 284         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 285         pmic_reg_write(p, REG_SW_2, val);
 286         udelay(50);
 287
 288         /* Raise the core frequency to 800MHz */
 289         writel(0x0, &mxc_ccm->cacrr);
 290
 291         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
 292         /* Setup the switcher mode for SW1 & SW2*/
 293         pmic_reg_read(p, REG_SW_4, &val);
 294         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 295                 (SWMODE_MASK << SWMODE2_SHIFT)));
 296         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 297                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 298         pmic_reg_write(p, REG_SW_4, val);
 299
 300         /* Setup the switcher mode for SW3 & SW4 */
 301         pmic_reg_read(p, REG_SW_5, &val);
 302         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 303                 (SWMODE_MASK << SWMODE4_SHIFT)));
 304         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 305                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
 306         pmic_reg_write(p, REG_SW_5, val);
 307
 308         /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
 309         pmic_reg_read(p, REG_SETTING_0, &val);
 310         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 311         val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
 312         pmic_reg_write(p, REG_SETTING_0, val);
 313
 314         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 315         pmic_reg_read(p, REG_SETTING_1, &val);
 316         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 317         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
 318         pmic_reg_write(p, REG_SETTING_1, val);
 319
 320         /* Configure VGEN3 and VCAM regulators to use external PNP */
 321         val = VGEN3CONFIG | VCAMCONFIG;
 322         pmic_reg_write(p, REG_MODE_1, val);
 323         udelay(200);
 324
 325         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 326         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 327                 VVIDEOEN | VAUDIOEN  | VSDEN;
 328         pmic_reg_write(p, REG_MODE_1, val);
 329
 330         mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1);
 331         gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
 332
 333         udelay(500);
 334
 335         gpio_set_value(IMX_GPIO_NR(2, 14), 1);
 336 }
 337
 338 #ifdef CONFIG_FSL_ESDHC
 339 int board_mmc_getcd(struct mmc *mmc)
 340 {
 341         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 342         int ret;
 343
 344         mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1);
 345         gpio_direction_input(IMX_GPIO_NR(1, 0));
 346         mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
 347         gpio_direction_input(IMX_GPIO_NR(1, 6));
 348
 349         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 350                 ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
 351         else
 352                 ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
 353
 354         return ret;
 355 }
 356
 357 int board_mmc_init(bd_t *bis)
 358 {
 359         u32 index;
 360         s32 status = 0;
 361
 362         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 363         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 364
 365         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 366                         index++) {
 367                 switch (index) {
 368                 case 0:
 369                         mxc_request_iomux(MX51_PIN_SD1_CMD,
 370                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 371                         mxc_request_iomux(MX51_PIN_SD1_CLK,
 372                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 373                         mxc_request_iomux(MX51_PIN_SD1_DATA0,
 374                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 375                         mxc_request_iomux(MX51_PIN_SD1_DATA1,
 376                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 377                         mxc_request_iomux(MX51_PIN_SD1_DATA2,
 378                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 379                         mxc_request_iomux(MX51_PIN_SD1_DATA3,
 380                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 381                         mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 382                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 383                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 384                                 PAD_CTL_PUE_PULL |
 385                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 386                         mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 387                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 388                                 PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
 389                                 PAD_CTL_PUE_PULL |
 390                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 391                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 392                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 393                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 394                                 PAD_CTL_PUE_PULL |
 395                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 396                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 397                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 398                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 399                                 PAD_CTL_PUE_PULL |
 400                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 401                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 402                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 403                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 404                                 PAD_CTL_PUE_PULL |
 405                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 406                         mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 407                                 PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
 408                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
 409                                 PAD_CTL_PUE_PULL |
 410                                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 411                         mxc_request_iomux(MX51_PIN_GPIO1_0,
 412                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 413                         mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
 414                                 PAD_CTL_HYS_ENABLE);
 415                         mxc_request_iomux(MX51_PIN_GPIO1_1,
 416                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 417                         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 418                                 PAD_CTL_HYS_ENABLE);
 419                         break;
 420                 case 1:
 421                         mxc_request_iomux(MX51_PIN_SD2_CMD,
 422                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 423                         mxc_request_iomux(MX51_PIN_SD2_CLK,
 424                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 425                         mxc_request_iomux(MX51_PIN_SD2_DATA0,
 426                                 IOMUX_CONFIG_ALT0);
 427                         mxc_request_iomux(MX51_PIN_SD2_DATA1,
 428                                 IOMUX_CONFIG_ALT0);
 429                         mxc_request_iomux(MX51_PIN_SD2_DATA2,
 430                                 IOMUX_CONFIG_ALT0);
 431                         mxc_request_iomux(MX51_PIN_SD2_DATA3,
 432                                 IOMUX_CONFIG_ALT0);
 433                         mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
 434                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 435                                 PAD_CTL_SRE_FAST);
 436                         mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
 437                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 438                                 PAD_CTL_SRE_FAST);
 439                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
 440                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 441                                 PAD_CTL_SRE_FAST);
 442                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
 443                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 444                                 PAD_CTL_SRE_FAST);
 445                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
 446                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 447                                 PAD_CTL_SRE_FAST);
 448                         mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
 449                                 PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
 450                                 PAD_CTL_SRE_FAST);
 451                         mxc_request_iomux(MX51_PIN_SD2_CMD,
 452                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 453                         mxc_request_iomux(MX51_PIN_GPIO1_6,
 454                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 455                         mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
 456                                 PAD_CTL_HYS_ENABLE);
 457                         mxc_request_iomux(MX51_PIN_GPIO1_5,
 458                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 459                         mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
 460                                 PAD_CTL_HYS_ENABLE);
 461                         break;
 462                 default:
 463                         printf("Warning: you configured more ESDHC controller"
 464                                 "(%d) as supported by the board(2)\n",
 465                                 CONFIG_SYS_FSL_ESDHC_NUM);
 466                         return status;
 467                 }
 468                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 469         }
 470         return status;
 471 }
 472 #endif
 473
 474 static struct fb_videomode const claa_wvga = {
 475         .name           = "CLAA07LC0ACW",
 476         .refresh        = 57,
 477         .xres           = 800,
 478         .yres           = 480,
 479         .pixclock       = 37037,
 480         .left_margin    = 40,
 481         .right_margin   = 60,
 482         .upper_margin   = 10,
 483         .lower_margin   = 10,
 484         .hsync_len      = 20,
 485         .vsync_len      = 10,
 486         .sync           = 0,
 487         .vmode          = FB_VMODE_NONINTERLACED
 488 };
 489
 490 void lcd_iomux(void)
 491 {
 492         /* DI2_PIN15 */
 493         mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);
 494
 495         /* Pad settings for MX51_PIN_DI2_DISP_CLK */
 496         mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
 497                           PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 498                           PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);
 499
 500         /* Turn on 3.3V voltage for LCD */
 501         mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
 502         gpio_direction_output(MX51EVK_LCD_3V3, 1);
 503
 504         /* Turn on 5V voltage for LCD */
 505         mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
 506         gpio_direction_output(MX51EVK_LCD_5V, 1);
 507
 508         /* Turn on GPIO backlight */
 509         mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
 510         mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
 511                                                         INPUT_CTL_PATH1);
 512         gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
 513 }
 514
 515 void lcd_enable(void)
 516 {
 517         int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
 518         if (ret)
 519                 printf("LCD cannot be configured: %d\n", ret);
 520 }
 521
 522 int board_early_init_f(void)
 523 {
 524         setup_iomux_uart();
 525         setup_iomux_fec();
 526 #ifdef CONFIG_USB_EHCI_MX5
 527         setup_usb_h1();
 528 #endif
 529         lcd_iomux();
 530
 531         return 0;
 532 }
 533
 534 int board_init(void)
 535 {
 536         /* address of boot parameters */
 537         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 538
 539         lcd_enable();
 540
 541         return 0;
 542 }
 543
 544 #ifdef CONFIG_BOARD_LATE_INIT
 545 int board_late_init(void)
 546 {
 547 #ifdef CONFIG_MXC_SPI
 548         setup_iomux_spi();
 549         power_init();
 550 #endif
 551
 552         return 0;
 553 }
 554 #endif
 555
 556 /*
 557  * Do not overwrite the console
 558  * Use always serial for U-Boot console
 559  */
 560 int overwrite_console(void)
 561 {
 562         return 1;
 563 }
 564
 565 int checkboard(void)
 566 {
 567         puts("Board: MX51EVK\n");
 568
 569         return 0;
 570 }