board/freescale/mpc8541cds/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/mmu.h>
  11
  12 struct fsl_e_tlb_entry tlb_table[] = {
  13         /* TLB 0 - for temp stack in cache */
  14         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  15                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16                       0, 0, BOOKE_PAGESZ_4K, 0),
  17         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  18                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19                       0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  25                       0, 0, BOOKE_PAGESZ_4K, 0),
  26
  27         /*
  28          * TLB 0:       16M     Non-cacheable, guarded
  29          * 0xff000000   16M     FLASH
  30          * Out of reset this entry is only 4K.
  31          */
  32         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
  33                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  34                       0, 0, BOOKE_PAGESZ_16M, 1),
  35
  36         /*
  37          * TLB 1:       256M    Non-cacheable, guarded
  38          * 0x80000000   256M    PCI1 MEM First half
  39          */
  40         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
  41                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  42                       0, 1, BOOKE_PAGESZ_256M, 1),
  43
  44         /*
  45          * TLB 2:       256M    Non-cacheable, guarded
  46          * 0x90000000   256M    PCI1 MEM Second half
  47          */
  48         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
  49                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  50                       0, 2, BOOKE_PAGESZ_256M, 1),
  51
  52         /*
  53          * TLB 3:       256M    Non-cacheable, guarded
  54          * 0xa0000000   256M    PCI2 MEM First half
  55          */
  56         SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
  57                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  58                       0, 3, BOOKE_PAGESZ_256M, 1),
  59
  60         /*
  61          * TLB 4:       256M    Non-cacheable, guarded
  62          * 0xb0000000   256M    PCI2 MEM Second half
  63          */
  64         SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
  65                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  66                       0, 4, BOOKE_PAGESZ_256M, 1),
  67
  68         /*
  69          * TLB 5:       64M     Non-cacheable, guarded
  70          * 0xe000_0000  1M      CCSRBAR
  71          * 0xe200_0000  16M     PCI1 IO
  72          * 0xe300_0000  16M     PCI2 IO
  73          */
  74         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  75                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  76                       0, 5, BOOKE_PAGESZ_64M, 1),
  77
  78         /*
  79          * TLB 6:       64M     Cacheable, non-guarded
  80          * 0xf000_0000  64M     LBC SDRAM
  81          */
  82         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
  83                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  84                       0, 6, BOOKE_PAGESZ_64M, 1),
  85
  86         /*
  87          * TLB 7:       1M      Non-cacheable, guarded
  88          * 0xf8000000   1M      CADMUS registers
  89          */
  90         SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
  91                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92                       0, 7, BOOKE_PAGESZ_1M, 1),
  93 };
  94
  95 int num_tlb_entries = ARRAY_SIZE(tlb_table);