board/freescale/mpc8541cds/law.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_law.h>
  11 #include <asm/mmu.h>
  12
  13 /*
  14  * LAW(Local Access Window) configuration:
  15  *
  16  * 0x0000_0000     0x7fff_ffff     DDR                     2G
  17  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
  18  * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
  19  * 0xe000_0000     0xe000_ffff     CCSR                    1M
  20  * 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
  21  * 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
  22  * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
  23  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
  24  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
  25  * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
  26  *
  27  * Notes:
  28  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  29  *    If flash is 8M at default position (last 8M), no LAW needed.
  30  */
  31
  32 struct law_entry law_table[] = {
  33         SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
  34         SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
  35         SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
  36         SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
  37         /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
  38         SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
  39 };
  40
  41 int num_law_entries = ARRAY_SIZE(law_table);