board/freescale/mpc8349emds/pci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <asm/mmu.h>
   7 #include <asm/io.h>
   8 #include <common.h>
   9 #include <mpc83xx.h>
  10 #include <pci.h>
  11 #include <i2c.h>
  12 #include <asm/fsl_i2c.h>
  13
  14 static struct pci_region pci1_regions[] = {
  15         {
  16                 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  17                 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  18                 size: CONFIG_SYS_PCI1_MEM_SIZE,
  19                 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  20         },
  21         {
  22                 bus_start: CONFIG_SYS_PCI1_IO_BASE,
  23                 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  24                 size: CONFIG_SYS_PCI1_IO_SIZE,
  25                 flags: PCI_REGION_IO
  26         },
  27         {
  28                 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  29                 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  30                 size: CONFIG_SYS_PCI1_MMIO_SIZE,
  31                 flags: PCI_REGION_MEM
  32         },
  33 };
  34
  35 #ifdef CONFIG_MPC83XX_PCI2
  36 static struct pci_region pci2_regions[] = {
  37         {
  38                 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
  39                 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
  40                 size: CONFIG_SYS_PCI2_MEM_SIZE,
  41                 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  42         },
  43         {
  44                 bus_start: CONFIG_SYS_PCI2_IO_BASE,
  45                 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
  46                 size: CONFIG_SYS_PCI2_IO_SIZE,
  47                 flags: PCI_REGION_IO
  48         },
  49         {
  50                 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
  51                 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
  52                 size: CONFIG_SYS_PCI2_MMIO_SIZE,
  53                 flags: PCI_REGION_MEM
  54         },
  55 };
  56 #endif
  57
  58 #ifndef CONFIG_PCISLAVE
  59 void pib_init(void)
  60 {
  61         u8 val8, orig_i2c_bus;
  62         /*
  63          * Assign PIB PMC slot to desired PCI bus
  64          */
  65         /* Switch temporarily to I2C bus #2 */
  66         orig_i2c_bus = i2c_get_bus_num();
  67         i2c_set_bus_num(1);
  68
  69         val8 = 0;
  70         i2c_write(0x23, 0x6, 1, &val8, 1);
  71         i2c_write(0x23, 0x7, 1, &val8, 1);
  72         val8 = 0xff;
  73         i2c_write(0x23, 0x2, 1, &val8, 1);
  74         i2c_write(0x23, 0x3, 1, &val8, 1);
  75
  76         val8 = 0;
  77         i2c_write(0x26, 0x6, 1, &val8, 1);
  78         val8 = 0x34;
  79         i2c_write(0x26, 0x7, 1, &val8, 1);
  80 #if defined(PCI_64BIT)
  81         val8 = 0xf4;    /* PMC2:PCI1/64-bit */
  82 #elif defined(PCI_ALL_PCI1)
  83         val8 = 0xf3;    /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
  84 #elif defined(PCI_ONE_PCI1)
  85         val8 = 0xf9;    /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
  86 #else
  87         val8 = 0xf5;    /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
  88 #endif
  89         i2c_write(0x26, 0x2, 1, &val8, 1);
  90         val8 = 0xff;
  91         i2c_write(0x26, 0x3, 1, &val8, 1);
  92         val8 = 0;
  93         i2c_write(0x27, 0x6, 1, &val8, 1);
  94         i2c_write(0x27, 0x7, 1, &val8, 1);
  95         val8 = 0xff;
  96         i2c_write(0x27, 0x2, 1, &val8, 1);
  97         val8 = 0xef;
  98         i2c_write(0x27, 0x3, 1, &val8, 1);
  99         asm("eieio");
 100
 101 #if defined(PCI_64BIT)
 102         printf("PCI1: 64-bit on PMC2\n");
 103 #elif defined(PCI_ALL_PCI1)
 104         printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
 105 #elif defined(PCI_ONE_PCI1)
 106         printf("PCI1: 32-bit on PMC1\n");
 107         printf("PCI2: 32-bit on PMC2, PMC3\n");
 108 #else
 109         printf("PCI1: 32-bit on PMC1, PMC2\n");
 110         printf("PCI2: 32-bit on PMC3\n");
 111 #endif
 112         /* Reset to original I2C bus */
 113         i2c_set_bus_num(orig_i2c_bus);
 114 }
 115
 116 void pci_init_board(void)
 117 {
 118         volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 119         volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 120         volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 121 #ifndef CONFIG_MPC83XX_PCI2
 122         struct pci_region *reg[] = { pci1_regions };
 123 #else
 124         struct pci_region *reg[] = { pci1_regions, pci2_regions };
 125 #endif
 126
 127         /* initialize the PCA9555PW IO expander on the PIB board */
 128         pib_init();
 129
 130         /* Enable all 8 PCI_CLK_OUTPUTS */
 131         clk->occr = 0xff000000;
 132         udelay(2000);
 133
 134         /* Configure PCI Local Access Windows */
 135         pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 136         pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 137
 138         pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 139         pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 140
 141         udelay(2000);
 142
 143 #ifndef CONFIG_MPC83XX_PCI2
 144         mpc83xx_pci_init(1, reg);
 145 #else
 146         mpc83xx_pci_init(2, reg);
 147 #endif
 148 }
 149
 150 #else
 151 void pci_init_board(void)
 152 {
 153         volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 154         volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 155         volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
 156         struct pci_region *reg[] = { pci1_regions };
 157
 158         /* Configure PCI Local Access Windows */
 159         pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 160         pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 161
 162         pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 163         pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 164
 165         mpc83xx_pci_init(1, reg);
 166
 167         /* Configure PCI Inbound Translation Windows (3 1MB windows) */
 168         pci_ctrl->pitar0 = 0x0;
 169         pci_ctrl->pibar0 = 0x0;
 170         pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
 171                            PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
 172
 173         pci_ctrl->pitar1  = 0x0;
 174         pci_ctrl->pibar1  = 0x0;
 175         pci_ctrl->piebar1 = 0x0;
 176         pci_ctrl->piwar1  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
 177                             PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
 178
 179         pci_ctrl->pitar2  = 0x0;
 180         pci_ctrl->pibar2  = 0x0;
 181         pci_ctrl->piebar2 = 0x0;
 182         pci_ctrl->piwar2  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
 183                             PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
 184
 185         /* Unlock the configuration bit */
 186         mpc83xx_pcislave_unlock(0);
 187         printf("PCI:   Agent mode enabled\n");
 188 }
 189 #endif /* CONFIG_PCISLAVE */