board/freescale/lx2160a/eth_lx2160ardb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018, 2020 NXP
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <fdt_support.h>
  10 #include <net.h>
  11 #include <netdev.h>
  12 #include <malloc.h>
  13 #include <fsl_mdio.h>
  14 #include <miiphy.h>
  15 #include <phy.h>
  16 #include <fm_eth.h>
  17 #include <asm/global_data.h>
  18 #include <asm/io.h>
  19 #include <exports.h>
  20 #include <asm/arch/fsl_serdes.h>
  21 #include <fsl-mc/fsl_mc.h>
  22 #include <fsl-mc/ldpaa_wriop.h>
  23 #include "lx2160a.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
  28 {
  29         int phy_reg;
  30         u32 phy_id;
  31
  32         phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  33         phy_id = (phy_reg & 0xffff) << 16;
  34
  35         phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  36         phy_id |= (phy_reg & 0xffff);
  37
  38         if (phy_id == PHY_UID_IN112525_S03)
  39                 return true;
  40         else
  41                 return false;
  42 }
  43
  44 int board_eth_init(struct bd_info *bis)
  45 {
  46 #if defined(CONFIG_FSL_MC_ENET)
  47         struct memac_mdio_info mdio_info;
  48         struct memac_mdio_controller *reg;
  49         int i, interface;
  50         struct mii_dev *dev;
  51         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  52         u32 srds_s1;
  53
  54         srds_s1 = in_le32(&gur->rcwsr[28]) &
  55                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  56         srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  57
  58         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  59         mdio_info.regs = reg;
  60         mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  61
  62         /* Register the EMI 1 */
  63         fm_memac_mdio_init(bis, &mdio_info);
  64
  65         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  66         mdio_info.regs = reg;
  67         mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  68
  69         /* Register the EMI 2 */
  70         fm_memac_mdio_init(bis, &mdio_info);
  71
  72         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  73         switch (srds_s1) {
  74         case 19:
  75                 wriop_set_phy_address(WRIOP1_DPMAC2, 0,
  76                                       CORTINA_PHY_ADDR1);
  77                 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
  78                                       AQR107_PHY_ADDR1);
  79                 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
  80                                       AQR107_PHY_ADDR2);
  81                 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
  82                         wriop_set_phy_address(WRIOP1_DPMAC5, 0,
  83                                               INPHI_PHY_ADDR1);
  84                         wriop_set_phy_address(WRIOP1_DPMAC6, 0,
  85                                               INPHI_PHY_ADDR1);
  86                 }
  87                 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
  88                                       RGMII_PHY_ADDR1);
  89                 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
  90                                       RGMII_PHY_ADDR2);
  91                 break;
  92
  93         case 18:
  94                 wriop_set_phy_address(WRIOP1_DPMAC7, 0,
  95                                       CORTINA_PHY_ADDR1);
  96                 wriop_set_phy_address(WRIOP1_DPMAC8, 0,
  97                                       CORTINA_PHY_ADDR1);
  98                 wriop_set_phy_address(WRIOP1_DPMAC9, 0,
  99                                       CORTINA_PHY_ADDR1);
 100                 wriop_set_phy_address(WRIOP1_DPMAC10, 0,
 101                                       CORTINA_PHY_ADDR1);
 102                 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
 103                                       AQR107_PHY_ADDR1);
 104                 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
 105                                       AQR107_PHY_ADDR2);
 106                 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
 107                         wriop_set_phy_address(WRIOP1_DPMAC5, 0,
 108                                               INPHI_PHY_ADDR1);
 109                         wriop_set_phy_address(WRIOP1_DPMAC6, 0,
 110                                               INPHI_PHY_ADDR1);
 111                 }
 112                 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
 113                                       RGMII_PHY_ADDR1);
 114                 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
 115                                       RGMII_PHY_ADDR2);
 116                 break;
 117
 118         default:
 119                 printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
 120                        srds_s1);
 121                 goto next;
 122         }
 123
 124         for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
 125                 interface = wriop_get_enet_if(i);
 126                 switch (interface) {
 127                 case PHY_INTERFACE_MODE_XGMII:
 128                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 129                         wriop_set_mdio(i, dev);
 130                         break;
 131                 case PHY_INTERFACE_MODE_25G_AUI:
 132                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 133                         wriop_set_mdio(i, dev);
 134                         break;
 135                 case PHY_INTERFACE_MODE_XLAUI:
 136                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 137                         wriop_set_mdio(i, dev);
 138                         break;
 139                 default:
 140                         break;
 141                 }
 142         }
 143         for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
 144                 interface = wriop_get_enet_if(i);
 145                 switch (interface) {
 146                 case PHY_INTERFACE_MODE_RGMII:
 147                 case PHY_INTERFACE_MODE_RGMII_ID:
 148                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 149                         wriop_set_mdio(i, dev);
 150                         break;
 151                 default:
 152                         break;
 153                 }
 154         }
 155
 156 next:
 157         cpu_eth_init(bis);
 158 #endif /* CONFIG_FSL_MC_ENET */
 159
 160 #ifdef CONFIG_PHY_AQUANTIA
 161         /*
 162          * Export functions to be used by AQ firmware
 163          * upload application
 164          */
 165         gd->jt->strcpy = strcpy;
 166         gd->jt->mdelay = mdelay;
 167         gd->jt->mdio_get_current_dev = mdio_get_current_dev;
 168         gd->jt->phy_find_by_mask = phy_find_by_mask;
 169         gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 170         gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 171 #endif
 172         return pci_eth_init(bis);
 173 }
 174
 175 #if defined(CONFIG_RESET_PHY_R)
 176 void reset_phy(void)
 177 {
 178 #if defined(CONFIG_FSL_MC_ENET)
 179         mc_env_boot();
 180 #endif
 181 }
 182 #endif /* CONFIG_RESET_PHY_R */
 183
 184 int fdt_fixup_board_phy(void *fdt)
 185 {
 186         int mdio_offset;
 187         int ret;
 188         struct mii_dev *dev;
 189
 190         ret = 0;
 191
 192         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 193         if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
 194                 mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
 195
 196                 if (mdio_offset < 0)
 197                         mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
 198
 199                 if (mdio_offset < 0) {
 200                         printf("mdio@0x8B9700 node not found in dts\n");
 201                         return mdio_offset;
 202                 }
 203
 204                 ret = fdt_setprop_string(fdt, mdio_offset, "status",
 205                                          "disabled");
 206                 if (ret) {
 207                         printf("Could not set disable mdio@0x8B97000 %s\n",
 208                                fdt_strerror(ret));
 209                         return ret;
 210                 }
 211         }
 212
 213         return ret;
 214 }