board/freescale/ls2080ardb/ls2080ardb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor
   4  * Copyright 2017, 2021 NXP
   5  */
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <display_options.h>
   9 #include <env.h>
  10 #include <init.h>
  11 #include <malloc.h>
  12 #include <errno.h>
  13 #include <netdev.h>
  14 #include <fsl_ifc.h>
  15 #include <fsl_ddr.h>
  16 #include <asm/global_data.h>
  17 #include <asm/io.h>
  18 #include <hwconfig.h>
  19 #include <fdt_support.h>
  20 #include <linux/libfdt.h>
  21 #include <fsl-mc/fsl_mc.h>
  22 #include <env_internal.h>
  23 #include <efi_loader.h>
  24 #include <i2c.h>
  25 #include <asm/arch/mmu.h>
  26 #include <asm/arch/soc.h>
  27 #include <asm/arch/ppa.h>
  28 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  29 #include "../common/i2c_mux.h"
  30
  31 #ifdef CONFIG_FSL_QIXIS
  32 #include "../common/qixis.h"
  33 #include "ls2080ardb_qixis.h"
  34 #endif
  35 #include "../common/vid.h"
  36
  37 #define CORTINA_FW_ADDR_IFCNOR                  0x580980000
  38 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK  0x584980000
  39 #define CORTINA_FW_ADDR_QSPI                    0x980000
  40 #define PIN_MUX_SEL_SDHC        0x00
  41 #define PIN_MUX_SEL_DSPI        0x0a
  42
  43 #define SET_SDHC_MUX_SEL(reg, value)    ((reg & 0xf0) | value)
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 enum {
  47         MUX_TYPE_SDHC,
  48         MUX_TYPE_DSPI,
  49 };
  50
  51 #ifdef CONFIG_VID
  52 u16 soc_get_fuse_vid(int vid_index)
  53 {
  54         static const u16 vdd[32] = {
  55                 10500,
  56                 0,      /* reserved */
  57                 9750,
  58                 0,      /* reserved */
  59                 9500,
  60                 0,      /* reserved */
  61                 0,      /* reserved */
  62                 0,      /* reserved */
  63                 9000,   /* reserved */
  64                 0,      /* reserved */
  65                 0,      /* reserved */
  66                 0,      /* reserved */
  67                 0,      /* reserved */
  68                 0,      /* reserved */
  69                 0,      /* reserved */
  70                 0,      /* reserved */
  71                 10000,  /* 1.0000V */
  72                 0,      /* reserved */
  73                 10250,
  74                 0,      /* reserved */
  75                 10500,
  76                 0,      /* reserved */
  77                 0,      /* reserved */
  78                 0,      /* reserved */
  79                 0,      /* reserved */
  80                 0,      /* reserved */
  81                 0,      /* reserved */
  82                 0,      /* reserved */
  83                 0,      /* reserved */
  84                 0,      /* reserved */
  85                 0,      /* reserved */
  86                 0,      /* reserved */
  87         };
  88
  89         return vdd[vid_index];
  90 };
  91 #endif
  92
  93 unsigned long long get_qixis_addr(void)
  94 {
  95         unsigned long long addr;
  96
  97         if (gd->flags & GD_FLG_RELOC)
  98                 addr = QIXIS_BASE_PHYS;
  99         else
 100                 addr = QIXIS_BASE_PHYS_EARLY;
 101
 102         /*
 103          * IFC address under 256MB is mapped to 0x30000000, any address above
 104          * is mapped to 0x5_10000000 up to 4GB.
 105          */
 106         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 107
 108         return addr;
 109 }
 110
 111 int checkboard(void)
 112 {
 113 #ifdef CONFIG_FSL_QIXIS
 114         u8 sw;
 115 #endif
 116         char buf[15];
 117
 118         cpu_name(buf);
 119         printf("Board: %s-RDB, ", buf);
 120
 121 #ifdef CONFIG_TARGET_LS2081ARDB
 122 #ifdef CONFIG_FSL_QIXIS
 123         sw = QIXIS_READ(arch);
 124         printf("Board version: %c, ", (sw & 0xf) + 'A');
 125
 126         sw = QIXIS_READ(brdcfg[0]);
 127         sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
 128         switch (sw) {
 129         case 0:
 130                 puts("boot from QSPI DEV#0\n");
 131                 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
 132                 break;
 133         case 1:
 134                 puts("boot from QSPI DEV#1\n");
 135                 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
 136                 break;
 137         case 2:
 138                 puts("boot from QSPI EMU\n");
 139                 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
 140                 break;
 141         case 3:
 142                 puts("boot from QSPI EMU\n");
 143                 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
 144                 break;
 145         case 4:
 146                 puts("boot from QSPI DEV#0\n");
 147                 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
 148                 break;
 149         default:
 150                 printf("invalid setting of SW%u\n", sw);
 151                 break;
 152         }
 153         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 154 #endif
 155         puts("SERDES1 Reference : ");
 156         printf("Clock1 = 100MHz ");
 157         printf("Clock2 = 161.13MHz");
 158 #else
 159 #ifdef CONFIG_FSL_QIXIS
 160         sw = QIXIS_READ(arch);
 161         printf("Board Arch: V%d, ", sw >> 4);
 162         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 163
 164         sw = QIXIS_READ(brdcfg[0]);
 165         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 166
 167         if (sw < 0x8)
 168                 printf("vBank: %d\n", sw);
 169         else if (sw == 0x9)
 170                 puts("NAND\n");
 171         else
 172                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 173
 174         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 175 #endif
 176         puts("SERDES1 Reference : ");
 177         printf("Clock1 = 156.25MHz ");
 178         printf("Clock2 = 156.25MHz");
 179 #endif
 180
 181         puts("\nSERDES2 Reference : ");
 182         printf("Clock1 = 100MHz ");
 183         printf("Clock2 = 100MHz\n");
 184
 185         return 0;
 186 }
 187
 188 unsigned long get_board_sys_clk(void)
 189 {
 190 #ifdef CONFIG_FSL_QIXIS
 191         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 192
 193         switch (sysclk_conf & 0x0F) {
 194         case QIXIS_SYSCLK_83:
 195                 return 83333333;
 196         case QIXIS_SYSCLK_100:
 197                 return 100000000;
 198         case QIXIS_SYSCLK_125:
 199                 return 125000000;
 200         case QIXIS_SYSCLK_133:
 201                 return 133333333;
 202         case QIXIS_SYSCLK_150:
 203                 return 150000000;
 204         case QIXIS_SYSCLK_160:
 205                 return 160000000;
 206         case QIXIS_SYSCLK_166:
 207                 return 166666666;
 208         }
 209 #endif
 210         return 100000000;
 211 }
 212
 213 int i2c_multiplexer_select_vid_channel(u8 channel)
 214 {
 215         return select_i2c_ch_pca9547(channel, 0);
 216 }
 217
 218 int config_board_mux(int ctrl_type)
 219 {
 220 #ifdef CONFIG_FSL_QIXIS
 221         u8 reg5;
 222
 223         reg5 = QIXIS_READ(brdcfg[5]);
 224
 225         switch (ctrl_type) {
 226         case MUX_TYPE_SDHC:
 227                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
 228                 break;
 229         case MUX_TYPE_DSPI:
 230                 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
 231                 break;
 232         default:
 233                 printf("Wrong mux interface type\n");
 234                 return -1;
 235         }
 236
 237         QIXIS_WRITE(brdcfg[5], reg5);
 238 #endif
 239         return 0;
 240 }
 241
 242 ulong *cs4340_get_fw_addr(void)
 243 {
 244 #ifdef CONFIG_TFABOOT
 245         struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 246         u32 svr = gur_in32(&gur->svr);
 247 #endif
 248         ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
 249
 250 #ifdef CONFIG_TFABOOT
 251         /* LS2088A TFA boot */
 252         if (SVR_SOC_VER(svr) == SVR_LS2088A) {
 253                 enum boot_src src = get_boot_src();
 254                 u8 sw;
 255
 256                 switch (src) {
 257                 case BOOT_SOURCE_IFC_NOR:
 258                         sw = QIXIS_READ(brdcfg[0]);
 259                         sw = (sw & 0x0f);
 260                         if (sw == 0)
 261                                 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
 262                         else if (sw == 4)
 263                                 cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
 264                         break;
 265                 case BOOT_SOURCE_QSPI_NOR:
 266                         /* Only one bank in QSPI */
 267                         cortina_fw_addr = CORTINA_FW_ADDR_QSPI;
 268                         break;
 269                 default:
 270                         printf("WARNING: Boot source not found\n");
 271                 }
 272         }
 273 #endif
 274         return (ulong *)cortina_fw_addr;
 275 }
 276
 277 int board_init(void)
 278 {
 279 #ifdef CONFIG_FSL_MC_ENET
 280         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 281 #endif
 282
 283         init_final_memctl_regs();
 284
 285         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 286
 287 #ifdef CONFIG_FSL_QIXIS
 288         QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 289 #endif
 290
 291 #ifdef CONFIG_FSL_LS_PPA
 292         ppa_init();
 293 #endif
 294
 295 #ifdef CONFIG_FSL_MC_ENET
 296         /* invert AQR405 IRQ pins polarity */
 297         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 298 #endif
 299
 300 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 301         pci_init();
 302 #endif
 303
 304         return 0;
 305 }
 306
 307 int board_early_init_f(void)
 308 {
 309 #if defined(CONFIG_SYS_I2C_EARLY_INIT)
 310         i2c_early_init_f();
 311 #endif
 312         fsl_lsch3_early_init_f();
 313         return 0;
 314 }
 315
 316 int misc_init_r(void)
 317 {
 318         char *env_hwconfig;
 319         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 320         u32 val;
 321         struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 322         u32 svr = gur_in32(&gur->svr);
 323
 324         val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
 325
 326         env_hwconfig = env_get("hwconfig");
 327
 328         if (hwconfig_f("dspi", env_hwconfig) &&
 329             DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
 330                 config_board_mux(MUX_TYPE_DSPI);
 331         else
 332                 config_board_mux(MUX_TYPE_SDHC);
 333
 334         /*
 335          * LS2081ARDB RevF board has smart voltage translator
 336          * which needs to be programmed to enable high speed SD interface
 337          * by setting GPIO4_10 output to zero
 338          */
 339 #ifdef CONFIG_TARGET_LS2081ARDB
 340                 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
 341                                             in_le32(GPIO4_GPDIR_ADDR)));
 342                 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
 343                                             in_le32(GPIO4_GPDAT_ADDR)));
 344 #endif
 345         if (hwconfig("sdhc"))
 346                 config_board_mux(MUX_TYPE_SDHC);
 347
 348         if (adjust_vdd(0))
 349                 printf("Warning: Adjusting core voltage failed.\n");
 350         /*
 351          * Default value of board env is based on filename which is
 352          * ls2080ardb. Modify board env for other supported SoCs
 353          */
 354         if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
 355             (SVR_SOC_VER(svr) == SVR_LS2048A))
 356                 env_set("board", "ls2088ardb");
 357         else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
 358             (SVR_SOC_VER(svr) == SVR_LS2041A))
 359                 env_set("board", "ls2081ardb");
 360
 361         return 0;
 362 }
 363
 364 void detail_board_ddr_info(void)
 365 {
 366         puts("\nDDR    ");
 367         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 368         print_ddr_info(0);
 369 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 370         if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
 371                 puts("\nDP-DDR ");
 372                 print_size(gd->bd->bi_dram[2].size, "");
 373                 print_ddr_info(CONFIG_DP_DDR_CTRL);
 374         }
 375 #endif
 376 }
 377
 378 #ifdef CONFIG_FSL_MC_ENET
 379 void fdt_fixup_board_enet(void *fdt)
 380 {
 381         int offset;
 382
 383         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 384
 385         if (offset < 0)
 386                 offset = fdt_path_offset(fdt, "/fsl-mc");
 387
 388         if (offset < 0) {
 389                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 390                        __func__, offset);
 391                 return;
 392         }
 393
 394         if (get_mc_boot_status() == 0 &&
 395             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 396                 fdt_status_okay(fdt, offset);
 397         else
 398                 fdt_status_fail(fdt, offset);
 399 }
 400
 401 void board_quiesce_devices(void)
 402 {
 403         fsl_mc_ldpaa_exit(gd->bd);
 404 }
 405 #endif
 406
 407 #ifdef CONFIG_OF_BOARD_SETUP
 408 void fsl_fdt_fixup_flash(void *fdt)
 409 {
 410         int offset;
 411 #ifdef CONFIG_TFABOOT
 412         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 413         u32 val;
 414 #endif
 415
 416 /*
 417  * IFC and QSPI are muxed on board.
 418  * So disable IFC node in dts if QSPI is enabled or
 419  * disable QSPI node in dts in case QSPI is not enabled.
 420  */
 421 #ifdef CONFIG_TFABOOT
 422         enum boot_src src = get_boot_src();
 423         bool disable_ifc = false;
 424
 425         switch (src) {
 426         case BOOT_SOURCE_IFC_NOR:
 427                 disable_ifc = false;
 428                 break;
 429         case BOOT_SOURCE_QSPI_NOR:
 430                 disable_ifc = true;
 431                 break;
 432         default:
 433                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 434                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 435                         disable_ifc = true;
 436                 break;
 437         }
 438
 439         if (disable_ifc) {
 440                 offset = fdt_path_offset(fdt, "/soc/ifc");
 441
 442                 if (offset < 0)
 443                         offset = fdt_path_offset(fdt, "/ifc");
 444         } else {
 445                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 446
 447                 if (offset < 0)
 448                         offset = fdt_path_offset(fdt, "/quadspi");
 449         }
 450
 451 #else
 452 #ifdef CONFIG_FSL_QSPI
 453         offset = fdt_path_offset(fdt, "/soc/ifc");
 454
 455         if (offset < 0)
 456                 offset = fdt_path_offset(fdt, "/ifc");
 457 #else
 458         offset = fdt_path_offset(fdt, "/soc/quadspi");
 459
 460         if (offset < 0)
 461                 offset = fdt_path_offset(fdt, "/quadspi");
 462 #endif
 463 #endif
 464
 465         if (offset < 0)
 466                 return;
 467
 468         fdt_status_disabled(fdt, offset);
 469 }
 470
 471 int ft_board_setup(void *blob, struct bd_info *bd)
 472 {
 473         int i;
 474         u16 mc_memory_bank = 0;
 475
 476         u64 *base;
 477         u64 *size;
 478         u64 mc_memory_base = 0;
 479         u64 mc_memory_size = 0;
 480         u16 total_memory_banks;
 481
 482         ft_cpu_setup(blob, bd);
 483
 484         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 485
 486         if (mc_memory_base != 0)
 487                 mc_memory_bank++;
 488
 489         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 490
 491         base = calloc(total_memory_banks, sizeof(u64));
 492         size = calloc(total_memory_banks, sizeof(u64));
 493
 494         /* fixup DT for the two GPP DDR banks */
 495         base[0] = gd->bd->bi_dram[0].start;
 496         size[0] = gd->bd->bi_dram[0].size;
 497         base[1] = gd->bd->bi_dram[1].start;
 498         size[1] = gd->bd->bi_dram[1].size;
 499
 500 #ifdef CONFIG_RESV_RAM
 501         /* reduce size if reserved memory is within this bank */
 502         if (gd->arch.resv_ram >= base[0] &&
 503             gd->arch.resv_ram < base[0] + size[0])
 504                 size[0] = gd->arch.resv_ram - base[0];
 505         else if (gd->arch.resv_ram >= base[1] &&
 506                  gd->arch.resv_ram < base[1] + size[1])
 507                 size[1] = gd->arch.resv_ram - base[1];
 508 #endif
 509
 510         if (mc_memory_base != 0) {
 511                 for (i = 0; i <= total_memory_banks; i++) {
 512                         if (base[i] == 0 && size[i] == 0) {
 513                                 base[i] = mc_memory_base;
 514                                 size[i] = mc_memory_size;
 515                                 break;
 516                         }
 517                 }
 518         }
 519
 520         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 521
 522         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 523
 524         fsl_fdt_fixup_dr_usb(blob, bd);
 525
 526         fsl_fdt_fixup_flash(blob);
 527
 528 #ifdef CONFIG_FSL_MC_ENET
 529         fdt_fixup_board_enet(blob);
 530 #endif
 531
 532         fdt_fixup_icid(blob);
 533
 534         return 0;
 535 }
 536 #endif
 537
 538 void qixis_dump_switch(void)
 539 {
 540 #ifdef CONFIG_FSL_QIXIS
 541         int i, nr_of_cfgsw;
 542
 543         QIXIS_WRITE(cms[0], 0x00);
 544         nr_of_cfgsw = QIXIS_READ(cms[1]);
 545
 546         puts("DIP switch settings dump:\n");
 547         for (i = 1; i <= nr_of_cfgsw; i++) {
 548                 QIXIS_WRITE(cms[0], i);
 549                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 550         }
 551 #endif
 552 }
 553
 554 /*
 555  * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 556  * Both slots has 0x54, resulting 2nd slot unusable.
 557  */
 558 void update_spd_address(unsigned int ctrl_num,
 559                         unsigned int slot,
 560                         unsigned int *addr)
 561 {
 562 #ifndef CONFIG_TARGET_LS2081ARDB
 563 #ifdef CONFIG_FSL_QIXIS
 564         u8 sw;
 565
 566         sw = QIXIS_READ(arch);
 567         if ((sw & 0xf) < 0x3) {
 568                 if (ctrl_num == 1 && slot == 0)
 569                         *addr = SPD_EEPROM_ADDRESS4;
 570                 else if (ctrl_num == 1 && slot == 1)
 571                         *addr = SPD_EEPROM_ADDRESS3;
 572         }
 573 #endif
 574 #endif
 575 }