board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2022 NXP
   4  */
   5 #include <common.h>
   6 #include <clock_legacy.h>
   7 #include <display_options.h>
   8 #include <env.h>
   9 #include <i2c.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <errno.h>
  14 #include <netdev.h>
  15 #include <fsl_ifc.h>
  16 #include <fsl_ddr.h>
  17 #include <asm/global_data.h>
  18 #include <asm/io.h>
  19 #include <fdt_support.h>
  20 #include <linux/delay.h>
  21 #include <linux/libfdt.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #include <env_internal.h>
  24 #include <asm/arch-fsl-layerscape/soc.h>
  25 #include <asm/arch/ppa.h>
  26 #include <hwconfig.h>
  27 #include <asm/arch/fsl_serdes.h>
  28 #include <asm/arch/soc.h>
  29 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  30 #include "../common/i2c_mux.h"
  31
  32 #include "../common/qixis.h"
  33 #include "ls1088a_qixis.h"
  34 #include "../common/vid.h"
  35 #include <fsl_immap.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifdef CONFIG_TARGET_LS1088AQDS
  40 #ifdef CONFIG_TFABOOT
  41 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  42         {
  43                 "nor0",
  44                 CONFIG_SYS_NOR0_CSPR_EARLY,
  45                 CONFIG_SYS_NOR0_CSPR_EXT,
  46                 CONFIG_SYS_NOR_AMASK,
  47                 CONFIG_SYS_NOR_CSOR,
  48                 {
  49                         CONFIG_SYS_NOR_FTIM0,
  50                         CONFIG_SYS_NOR_FTIM1,
  51                         CONFIG_SYS_NOR_FTIM2,
  52                         CONFIG_SYS_NOR_FTIM3
  53                 },
  54                 0,
  55                 CONFIG_SYS_NOR0_CSPR,
  56                 0,
  57         },
  58         {
  59                 "nor1",
  60                 CONFIG_SYS_NOR1_CSPR_EARLY,
  61                 CONFIG_SYS_NOR0_CSPR_EXT,
  62                 CONFIG_SYS_NOR_AMASK_EARLY,
  63                 CONFIG_SYS_NOR_CSOR,
  64                 {
  65                         CONFIG_SYS_NOR_FTIM0,
  66                         CONFIG_SYS_NOR_FTIM1,
  67                         CONFIG_SYS_NOR_FTIM2,
  68                         CONFIG_SYS_NOR_FTIM3
  69                 },
  70                 0,
  71                 CONFIG_SYS_NOR1_CSPR,
  72                 CONFIG_SYS_NOR_AMASK,
  73         },
  74         {
  75                 "nand",
  76                 CONFIG_SYS_NAND_CSPR,
  77                 CONFIG_SYS_NAND_CSPR_EXT,
  78                 CONFIG_SYS_NAND_AMASK,
  79                 CONFIG_SYS_NAND_CSOR,
  80                 {
  81                         CONFIG_SYS_NAND_FTIM0,
  82                         CONFIG_SYS_NAND_FTIM1,
  83                         CONFIG_SYS_NAND_FTIM2,
  84                         CONFIG_SYS_NAND_FTIM3
  85                 },
  86         },
  87         {
  88                 "fpga",
  89                 CONFIG_SYS_FPGA_CSPR,
  90                 CONFIG_SYS_FPGA_CSPR_EXT,
  91                 SYS_FPGA_AMASK,
  92                 CONFIG_SYS_FPGA_CSOR,
  93                 {
  94                         SYS_FPGA_CS_FTIM0,
  95                         SYS_FPGA_CS_FTIM1,
  96                         SYS_FPGA_CS_FTIM2,
  97                         SYS_FPGA_CS_FTIM3
  98                 },
  99                 0,
 100                 SYS_FPGA_CSPR_FINAL,
 101                 0,
 102         }
 103 };
 104
 105 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 106         {
 107                 "nand",
 108                 CONFIG_SYS_NAND_CSPR,
 109                 CONFIG_SYS_NAND_CSPR_EXT,
 110                 CONFIG_SYS_NAND_AMASK,
 111                 CONFIG_SYS_NAND_CSOR,
 112                 {
 113                         CONFIG_SYS_NAND_FTIM0,
 114                         CONFIG_SYS_NAND_FTIM1,
 115                         CONFIG_SYS_NAND_FTIM2,
 116                         CONFIG_SYS_NAND_FTIM3
 117                 },
 118         },
 119         {
 120                 "reserved",
 121         },
 122         {
 123                 "fpga",
 124                 CONFIG_SYS_FPGA_CSPR,
 125                 CONFIG_SYS_FPGA_CSPR_EXT,
 126                 SYS_FPGA_AMASK,
 127                 CONFIG_SYS_FPGA_CSOR,
 128                 {
 129                         SYS_FPGA_CS_FTIM0,
 130                         SYS_FPGA_CS_FTIM1,
 131                         SYS_FPGA_CS_FTIM2,
 132                         SYS_FPGA_CS_FTIM3
 133                 },
 134                 0,
 135                 SYS_FPGA_CSPR_FINAL,
 136                 0,
 137         }
 138 };
 139
 140 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 141 {
 142         enum boot_src src = get_boot_src();
 143
 144         if (src == BOOT_SOURCE_QSPI_NOR)
 145                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 146         else
 147                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 148
 149         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 150 }
 151 #endif /* CONFIG_TFABOOT */
 152 #endif /* CONFIG_TARGET_LS1088AQDS */
 153
 154 int board_early_init_f(void)
 155 {
 156 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 157         i2c_early_init_f();
 158 #endif
 159         fsl_lsch3_early_init_f();
 160         return 0;
 161 }
 162
 163 #ifdef CONFIG_FSL_QIXIS
 164 unsigned long long get_qixis_addr(void)
 165 {
 166         unsigned long long addr;
 167
 168         if (gd->flags & GD_FLG_RELOC)
 169                 addr = QIXIS_BASE_PHYS;
 170         else
 171                 addr = QIXIS_BASE_PHYS_EARLY;
 172
 173         /*
 174          * IFC address under 256MB is mapped to 0x30000000, any address above
 175          * is mapped to 0x5_10000000 up to 4GB.
 176          */
 177         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 178
 179         return addr;
 180 }
 181 #endif
 182
 183 #if defined(CONFIG_VID)
 184 int init_func_vid(void)
 185 {
 186         if (adjust_vdd(0) < 0)
 187                 printf("core voltage not adjusted\n");
 188
 189         return 0;
 190 }
 191
 192 u16 soc_get_fuse_vid(int vid_index)
 193 {
 194         static const u16 vdd[32] = {
 195                 10250,
 196                 9875,
 197                 9750,
 198                 0,      /* reserved */
 199                 0,      /* reserved */
 200                 0,      /* reserved */
 201                 0,      /* reserved */
 202                 0,      /* reserved */
 203                 9000,
 204                 0,      /* reserved */
 205                 0,      /* reserved */
 206                 0,      /* reserved */
 207                 0,      /* reserved */
 208                 0,      /* reserved */
 209                 0,      /* reserved */
 210                 0,      /* reserved */
 211                 10000,  /* 1.0000V */
 212                 10125,
 213                 10250,
 214                 0,      /* reserved */
 215                 0,      /* reserved */
 216                 0,      /* reserved */
 217                 0,      /* reserved */
 218                 0,      /* reserved */
 219                 0,      /* reserved */
 220                 0,      /* reserved */
 221                 0,      /* reserved */
 222                 0,      /* reserved */
 223                 0,      /* reserved */
 224                 0,      /* reserved */
 225                 0,      /* reserved */
 226                 0,      /* reserved */
 227         };
 228
 229         return vdd[vid_index];
 230 };
 231 #endif
 232
 233 int is_pb_board(void)
 234 {
 235         u8 board_id;
 236
 237         board_id = QIXIS_READ(id);
 238         if (board_id == LS1088ARDB_PB_BOARD)
 239                 return 1;
 240         else
 241                 return 0;
 242 }
 243
 244 int fixup_ls1088ardb_pb_banner(void *fdt)
 245 {
 246         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 247
 248         return 0;
 249 }
 250
 251 #if !defined(CONFIG_SPL_BUILD)
 252 int checkboard(void)
 253 {
 254 #ifdef CONFIG_TFABOOT
 255         enum boot_src src = get_boot_src();
 256 #endif
 257         char buf[64];
 258         u8 sw;
 259         static const char *const freq[] = {"100", "125", "156.25",
 260                                             "100 separate SSCG"};
 261         int clock;
 262
 263 #ifdef CONFIG_TARGET_LS1088AQDS
 264         printf("Board: LS1088A-QDS, ");
 265 #else
 266         if (is_pb_board())
 267                 printf("Board: LS1088ARDB-PB, ");
 268         else
 269                 printf("Board: LS1088A-RDB, ");
 270 #endif
 271
 272         sw = QIXIS_READ(arch);
 273         printf("Board Arch: V%d, ", sw >> 4);
 274
 275 #ifdef CONFIG_TARGET_LS1088AQDS
 276         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 277 #else
 278         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 279 #endif
 280
 281         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 282
 283         sw = QIXIS_READ(brdcfg[0]);
 284         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 285
 286 #ifdef CONFIG_TFABOOT
 287         if (src == BOOT_SOURCE_SD_MMC)
 288                 puts("SD card\n");
 289 #else
 290 #ifdef CONFIG_SD_BOOT
 291         puts("SD card\n");
 292 #endif
 293 #endif /* CONFIG_TFABOOT */
 294         switch (sw) {
 295 #ifdef CONFIG_TARGET_LS1088AQDS
 296         case 0:
 297         case 1:
 298         case 2:
 299         case 3:
 300         case 4:
 301         case 5:
 302         case 6:
 303         case 7:
 304                 printf("vBank: %d\n", sw);
 305                 break;
 306         case 8:
 307                 puts("PromJet\n");
 308                 break;
 309         case 15:
 310                 puts("IFCCard\n");
 311                 break;
 312         case 14:
 313 #else
 314         case 0:
 315 #endif
 316                 puts("QSPI:");
 317                 sw = QIXIS_READ(brdcfg[0]);
 318                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 319                 if (sw == 0 || sw == 4)
 320                         puts("0\n");
 321                 else if (sw == 1)
 322                         puts("1\n");
 323                 else
 324                         puts("EMU\n");
 325                 break;
 326
 327         default:
 328                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 329                 break;
 330         }
 331
 332 #ifdef CONFIG_TARGET_LS1088AQDS
 333         printf("FPGA: v%d (%s), build %d",
 334                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 335                (int)qixis_read_minor());
 336         /* the timestamp string contains "\n" at the end */
 337         printf(" on %s", qixis_read_time(buf));
 338 #else
 339         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 340 #endif
 341
 342         /*
 343          * Display the actual SERDES reference clocks as configured by the
 344          * dip switches on the board.  Note that the SWx registers could
 345          * technically be set to force the reference clocks to match the
 346          * values that the SERDES expects (or vice versa).  For now, however,
 347          * we just display both values and hope the user notices when they
 348          * don't match.
 349          */
 350         puts("SERDES1 Reference : ");
 351         sw = QIXIS_READ(brdcfg[2]);
 352         clock = (sw >> 6) & 3;
 353         printf("Clock1 = %sMHz ", freq[clock]);
 354         clock = (sw >> 4) & 3;
 355         printf("Clock2 = %sMHz", freq[clock]);
 356
 357         puts("\nSERDES2 Reference : ");
 358         clock = (sw >> 2) & 3;
 359         printf("Clock1 = %sMHz ", freq[clock]);
 360         clock = (sw >> 0) & 3;
 361         printf("Clock2 = %sMHz\n", freq[clock]);
 362
 363         return 0;
 364 }
 365 #endif
 366
 367 bool if_board_diff_clk(void)
 368 {
 369 #ifdef CONFIG_TARGET_LS1088AQDS
 370         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 371         return diff_conf & 0x40;
 372 #else
 373         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 374         return diff_conf & 0x80;
 375 #endif
 376 }
 377
 378 #ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
 379 unsigned long get_board_sys_clk(void)
 380 {
 381         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 382
 383         switch (sysclk_conf & 0x0f) {
 384         case QIXIS_SYSCLK_83:
 385                 return 83333333;
 386         case QIXIS_SYSCLK_100:
 387                 return 100000000;
 388         case QIXIS_SYSCLK_125:
 389                 return 125000000;
 390         case QIXIS_SYSCLK_133:
 391                 return 133333333;
 392         case QIXIS_SYSCLK_150:
 393                 return 150000000;
 394         case QIXIS_SYSCLK_160:
 395                 return 160000000;
 396         case QIXIS_SYSCLK_166:
 397                 return 166666666;
 398         }
 399
 400         return 66666666;
 401 }
 402 #endif
 403
 404 #ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
 405 unsigned long get_board_ddr_clk(void)
 406 {
 407         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 408
 409         if (if_board_diff_clk())
 410                 return get_board_sys_clk();
 411         switch ((ddrclk_conf & 0x30) >> 4) {
 412         case QIXIS_DDRCLK_100:
 413                 return 100000000;
 414         case QIXIS_DDRCLK_125:
 415                 return 125000000;
 416         case QIXIS_DDRCLK_133:
 417                 return 133333333;
 418         }
 419
 420         return 66666666;
 421 }
 422 #endif
 423
 424 #if !defined(CONFIG_SPL_BUILD)
 425 void board_retimer_init(void)
 426 {
 427         u8 reg;
 428
 429         /* Retimer is connected to I2C1_CH5 */
 430         select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
 431
 432         /* Access to Control/Shared register */
 433         reg = 0x0;
 434 #if !CONFIG_IS_ENABLED(DM_I2C)
 435         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 436 #else
 437         struct udevice *dev;
 438
 439         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 440         dm_i2c_write(dev, 0xff, &reg, 1);
 441 #endif
 442
 443         /* Read device revision and ID */
 444 #if !CONFIG_IS_ENABLED(DM_I2C)
 445         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 446 #else
 447         dm_i2c_read(dev, 1, &reg, 1);
 448 #endif
 449         debug("Retimer version id = 0x%x\n", reg);
 450
 451         /* Enable Broadcast. All writes target all channel register sets */
 452         reg = 0x0c;
 453 #if !CONFIG_IS_ENABLED(DM_I2C)
 454         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 455 #else
 456         dm_i2c_write(dev, 0xff, &reg, 1);
 457 #endif
 458
 459         /* Reset Channel Registers */
 460 #if !CONFIG_IS_ENABLED(DM_I2C)
 461         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 462 #else
 463         dm_i2c_read(dev, 0, &reg, 1);
 464 #endif
 465         reg |= 0x4;
 466 #if !CONFIG_IS_ENABLED(DM_I2C)
 467         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 468 #else
 469         dm_i2c_write(dev, 0, &reg, 1);
 470 #endif
 471
 472         /* Set data rate as 10.3125 Gbps */
 473         reg = 0x90;
 474 #if !CONFIG_IS_ENABLED(DM_I2C)
 475         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 476 #else
 477         dm_i2c_write(dev, 0x60, &reg, 1);
 478 #endif
 479         reg = 0xb3;
 480 #if !CONFIG_IS_ENABLED(DM_I2C)
 481         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 482 #else
 483         dm_i2c_write(dev, 0x61, &reg, 1);
 484 #endif
 485         reg = 0x90;
 486 #if !CONFIG_IS_ENABLED(DM_I2C)
 487         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 488 #else
 489         dm_i2c_write(dev, 0x62, &reg, 1);
 490 #endif
 491         reg = 0xb3;
 492 #if !CONFIG_IS_ENABLED(DM_I2C)
 493         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 494 #else
 495         dm_i2c_write(dev, 0x63, &reg, 1);
 496 #endif
 497         reg = 0xcd;
 498 #if !CONFIG_IS_ENABLED(DM_I2C)
 499         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 500 #else
 501         dm_i2c_write(dev, 0x64, &reg, 1);
 502 #endif
 503
 504         /* Select VCO Divider to full rate (000) */
 505 #if !CONFIG_IS_ENABLED(DM_I2C)
 506         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 507 #else
 508         dm_i2c_read(dev, 0x2F, &reg, 1);
 509 #endif
 510         reg &= 0x0f;
 511         reg |= 0x70;
 512 #if !CONFIG_IS_ENABLED(DM_I2C)
 513         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 514 #else
 515         dm_i2c_write(dev, 0x2F, &reg, 1);
 516 #endif
 517
 518 #ifdef  CONFIG_TARGET_LS1088AQDS
 519         /* Retimer is connected to I2C1_CH5 */
 520         select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
 521
 522         /* Access to Control/Shared register */
 523         reg = 0x0;
 524 #if !CONFIG_IS_ENABLED(DM_I2C)
 525         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 526 #else
 527         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 528         dm_i2c_write(dev, 0xff, &reg, 1);
 529 #endif
 530
 531         /* Read device revision and ID */
 532 #if !CONFIG_IS_ENABLED(DM_I2C)
 533         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 534 #else
 535         dm_i2c_read(dev, 1, &reg, 1);
 536 #endif
 537         debug("Retimer version id = 0x%x\n", reg);
 538
 539         /* Enable Broadcast. All writes target all channel register sets */
 540         reg = 0x0c;
 541 #if !CONFIG_IS_ENABLED(DM_I2C)
 542         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 543 #else
 544         dm_i2c_write(dev, 0xff, &reg, 1);
 545 #endif
 546
 547         /* Reset Channel Registers */
 548 #if !CONFIG_IS_ENABLED(DM_I2C)
 549         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 550 #else
 551         dm_i2c_read(dev, 0, &reg, 1);
 552 #endif
 553         reg |= 0x4;
 554 #if !CONFIG_IS_ENABLED(DM_I2C)
 555         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 556 #else
 557         dm_i2c_write(dev, 0, &reg, 1);
 558 #endif
 559
 560         /* Set data rate as 10.3125 Gbps */
 561         reg = 0x90;
 562 #if !CONFIG_IS_ENABLED(DM_I2C)
 563         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 564 #else
 565         dm_i2c_write(dev, 0x60, &reg, 1);
 566 #endif
 567         reg = 0xb3;
 568 #if !CONFIG_IS_ENABLED(DM_I2C)
 569         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 570 #else
 571         dm_i2c_write(dev, 0x61, &reg, 1);
 572 #endif
 573         reg = 0x90;
 574 #if !CONFIG_IS_ENABLED(DM_I2C)
 575         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 576 #else
 577         dm_i2c_write(dev, 0x62, &reg, 1);
 578 #endif
 579         reg = 0xb3;
 580 #if !CONFIG_IS_ENABLED(DM_I2C)
 581         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 582 #else
 583         dm_i2c_write(dev, 0x63, &reg, 1);
 584 #endif
 585         reg = 0xcd;
 586 #if !CONFIG_IS_ENABLED(DM_I2C)
 587         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 588 #else
 589         dm_i2c_write(dev, 0x64, &reg, 1);
 590 #endif
 591
 592         /* Select VCO Divider to full rate (000) */
 593 #if !CONFIG_IS_ENABLED(DM_I2C)
 594         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 595 #else
 596         dm_i2c_read(dev, 0x2F, &reg, 1);
 597 #endif
 598         reg &= 0x0f;
 599         reg |= 0x70;
 600 #if !CONFIG_IS_ENABLED(DM_I2C)
 601         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 602 #else
 603         dm_i2c_write(dev, 0x2F, &reg, 1);
 604 #endif
 605
 606 #endif
 607         /*return the default channel*/
 608         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 609 }
 610
 611 #ifdef CONFIG_MISC_INIT_R
 612 int misc_init_r(void)
 613 {
 614 #ifdef CONFIG_TARGET_LS1088ARDB
 615         u8 brdcfg5;
 616
 617         if (hwconfig("esdhc-force-sd")) {
 618                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 619                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 620                 brdcfg5 |= BRDCFG5_FORCE_SD;
 621                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 622         }
 623 #endif
 624
 625 #ifdef CONFIG_TARGET_LS1088AQDS
 626          u8 brdcfg4, brdcfg5;
 627
 628         if (hwconfig("dspi-on-board")) {
 629                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 630                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 631                 brdcfg4 |= BRDCFG4_SPI;
 632                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 633
 634                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 635                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 636                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 637                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 638         } else if (hwconfig("dspi-off-board")) {
 639                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 640                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 641                 brdcfg4 |= BRDCFG4_SPI;
 642                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 643
 644                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 645                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 646                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 647                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 648         }
 649 #endif
 650         return 0;
 651 }
 652 #endif
 653 #endif
 654
 655 int i2c_multiplexer_select_vid_channel(u8 channel)
 656 {
 657         return select_i2c_ch_pca9547(channel, 0);
 658 }
 659
 660 #ifdef CONFIG_TARGET_LS1088AQDS
 661 /* read the current value(SVDD) of the LTM Regulator Voltage */
 662 int get_serdes_volt(void)
 663 {
 664         int  ret, vcode = 0;
 665         u8 chan = PWM_CHANNEL0;
 666
 667         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 668 #if !CONFIG_IS_ENABLED(DM_I2C)
 669         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 670                         PMBUS_CMD_PAGE, 1, &chan, 1);
 671 #else
 672         struct udevice *dev;
 673
 674         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 675         if (!ret)
 676                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 677                                    &chan, 1);
 678 #endif
 679
 680         if (ret) {
 681                 printf("VID: failed to select VDD Page 0\n");
 682                 return ret;
 683         }
 684
 685         /* Read the output voltage using PMBus command READ_VOUT */
 686 #if !CONFIG_IS_ENABLED(DM_I2C)
 687         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 688                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 689 #else
 690         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 691 #endif
 692         if (ret) {
 693                 printf("VID: failed to read the volatge\n");
 694                 return ret;
 695         }
 696
 697         return vcode;
 698 }
 699
 700 int set_serdes_volt(int svdd)
 701 {
 702         int ret, vdd_last;
 703         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 704                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 705
 706         /* Write the desired voltage code to the SVDD regulator */
 707 #if !CONFIG_IS_ENABLED(DM_I2C)
 708         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 709                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 710 #else
 711         struct udevice *dev;
 712
 713         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 714         if (!ret)
 715                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 716                                    (void *)&buff, 5);
 717 #endif
 718         if (ret) {
 719                 printf("VID: I2C failed to write to the volatge regulator\n");
 720                 return -1;
 721         }
 722
 723         /* Wait for the volatge to get to the desired value */
 724         do {
 725                 vdd_last = get_serdes_volt();
 726                 if (vdd_last < 0) {
 727                         printf("VID: Couldn't read sensor abort VID adjust\n");
 728                         return -1;
 729                 }
 730         } while (vdd_last != svdd);
 731
 732         return 1;
 733 }
 734 #else
 735 int get_serdes_volt(void)
 736 {
 737         return 0;
 738 }
 739
 740 int set_serdes_volt(int svdd)
 741 {
 742         int ret;
 743         u8 brdcfg4;
 744
 745         printf("SVDD changing of RDB\n");
 746
 747         /* Read the BRDCFG54 via CLPD */
 748 #if !CONFIG_IS_ENABLED(DM_I2C)
 749         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 750                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 751 #else
 752         struct udevice *dev;
 753
 754         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 755         if (!ret)
 756                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 757                                   (void *)&brdcfg4, 1);
 758 #endif
 759
 760         if (ret) {
 761                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 762                 return -1;
 763         }
 764
 765         brdcfg4 = brdcfg4 | 0x08;
 766
 767         /* Write to the BRDCFG4 */
 768 #if !CONFIG_IS_ENABLED(DM_I2C)
 769         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 770                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 771 #else
 772         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 773                            (void *)&brdcfg4, 1);
 774 #endif
 775
 776         if (ret) {
 777                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 778                 return -1;
 779         }
 780
 781         /* Wait for the volatge to get to the desired value */
 782         udelay(10000);
 783
 784         return 1;
 785 }
 786 #endif
 787
 788 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 789 int board_adjust_vdd(int vdd)
 790 {
 791         int ret = 0;
 792
 793         debug("%s: vdd = %d\n", __func__, vdd);
 794
 795         /* Special settings to be performed when voltage is 900mV */
 796         if (vdd == 900) {
 797                 ret = setup_serdes_volt(vdd);
 798                 if (ret < 0) {
 799                         ret = -1;
 800                         goto exit;
 801                 }
 802         }
 803 exit:
 804         return ret;
 805 }
 806
 807 #if !defined(CONFIG_SPL_BUILD)
 808 int board_init(void)
 809 {
 810         init_final_memctl_regs();
 811 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 812         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 813 #endif
 814
 815         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 816         board_retimer_init();
 817
 818 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 819         /* invert AQR105 IRQ pins polarity */
 820         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 821 #endif
 822
 823 #ifdef CONFIG_FSL_LS_PPA
 824         ppa_init();
 825 #endif
 826
 827 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 828         pci_init();
 829 #endif
 830
 831         return 0;
 832 }
 833
 834 void detail_board_ddr_info(void)
 835 {
 836         puts("\nDDR    ");
 837         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 838         print_ddr_info(0);
 839 }
 840
 841 #ifdef CONFIG_FSL_MC_ENET
 842 void board_quiesce_devices(void)
 843 {
 844         fsl_mc_ldpaa_exit(gd->bd);
 845 }
 846
 847 void fdt_fixup_board_enet(void *fdt)
 848 {
 849         int offset;
 850
 851         offset = fdt_path_offset(fdt, "/fsl-mc");
 852
 853         if (offset < 0)
 854                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 855
 856         if (offset < 0) {
 857                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 858                        __func__, offset);
 859                 return;
 860         }
 861
 862         if (get_mc_boot_status() == 0 &&
 863             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 864                 fdt_status_okay(fdt, offset);
 865         else
 866                 fdt_status_fail(fdt, offset);
 867 }
 868 #endif
 869
 870 #ifdef CONFIG_OF_BOARD_SETUP
 871 void fsl_fdt_fixup_flash(void *fdt)
 872 {
 873         int offset;
 874 #ifdef CONFIG_TFABOOT
 875         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 876         u32 val;
 877 #endif
 878
 879 /*
 880  * IFC-NOR and QSPI are muxed on SoC.
 881  * So disable IFC node in dts if QSPI is enabled or
 882  * disable QSPI node in dts in case QSPI is not enabled.
 883  */
 884
 885 #ifdef CONFIG_TFABOOT
 886         enum boot_src src = get_boot_src();
 887         bool disable_ifc = false;
 888
 889         switch (src) {
 890         case BOOT_SOURCE_IFC_NOR:
 891                 disable_ifc = false;
 892                 break;
 893         case BOOT_SOURCE_QSPI_NOR:
 894                 disable_ifc = true;
 895                 break;
 896         default:
 897                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 898                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 899                         disable_ifc = true;
 900                 break;
 901         }
 902
 903         if (disable_ifc) {
 904                 offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
 905
 906                 if (offset < 0)
 907                         offset = fdt_path_offset(fdt, "/memory-controller/nor");
 908         } else {
 909                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 910
 911                 if (offset < 0)
 912                         offset = fdt_path_offset(fdt, "/quadspi");
 913         }
 914
 915 #else
 916 #ifdef CONFIG_FSL_QSPI
 917         offset = fdt_path_offset(fdt, "/soc/memory-controller/nor");
 918
 919         if (offset < 0)
 920                 offset = fdt_path_offset(fdt, "/memory-controller/nor");
 921 #else
 922         offset = fdt_path_offset(fdt, "/soc/quadspi");
 923
 924         if (offset < 0)
 925                 offset = fdt_path_offset(fdt, "/quadspi");
 926 #endif
 927 #endif
 928         if (offset < 0)
 929                 return;
 930
 931         fdt_status_disabled(fdt, offset);
 932 }
 933
 934 int ft_board_setup(void *blob, struct bd_info *bd)
 935 {
 936         int i;
 937         u16 mc_memory_bank = 0;
 938
 939         u64 *base;
 940         u64 *size;
 941         u64 mc_memory_base = 0;
 942         u64 mc_memory_size = 0;
 943         u16 total_memory_banks;
 944
 945         ft_cpu_setup(blob, bd);
 946
 947         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 948
 949         if (mc_memory_base != 0)
 950                 mc_memory_bank++;
 951
 952         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 953
 954         base = calloc(total_memory_banks, sizeof(u64));
 955         size = calloc(total_memory_banks, sizeof(u64));
 956
 957         /* fixup DT for the two GPP DDR banks */
 958         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 959                 base[i] = gd->bd->bi_dram[i].start;
 960                 size[i] = gd->bd->bi_dram[i].size;
 961         }
 962
 963 #ifdef CONFIG_RESV_RAM
 964         /* reduce size if reserved memory is within this bank */
 965         if (gd->arch.resv_ram >= base[0] &&
 966             gd->arch.resv_ram < base[0] + size[0])
 967                 size[0] = gd->arch.resv_ram - base[0];
 968         else if (gd->arch.resv_ram >= base[1] &&
 969                  gd->arch.resv_ram < base[1] + size[1])
 970                 size[1] = gd->arch.resv_ram - base[1];
 971 #endif
 972
 973         if (mc_memory_base != 0) {
 974                 for (i = 0; i <= total_memory_banks; i++) {
 975                         if (base[i] == 0 && size[i] == 0) {
 976                                 base[i] = mc_memory_base;
 977                                 size[i] = mc_memory_size;
 978                                 break;
 979                         }
 980                 }
 981         }
 982
 983         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 984
 985         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 986
 987         fsl_fdt_fixup_flash(blob);
 988
 989 #ifdef CONFIG_FSL_MC_ENET
 990         fdt_fixup_board_enet(blob);
 991 #endif
 992
 993         fdt_fixup_icid(blob);
 994
 995         if (is_pb_board())
 996                 fixup_ls1088ardb_pb_banner(blob);
 997
 998         return 0;
 999 }
1000 #endif
1001 #endif /* defined(CONFIG_SPL_BUILD) */
1002
1003 #ifdef CONFIG_TFABOOT
1004 #ifdef CONFIG_MTD_NOR_FLASH
1005 int is_flash_available(void)
1006 {
1007         char *env_hwconfig = env_get("hwconfig");
1008         enum boot_src src = get_boot_src();
1009         int is_nor_flash_available = 1;
1010
1011         switch (src) {
1012         case BOOT_SOURCE_IFC_NOR:
1013                 is_nor_flash_available = 1;
1014                 break;
1015         case BOOT_SOURCE_QSPI_NOR:
1016                 is_nor_flash_available = 0;
1017                 break;
1018         /*
1019          * In Case of SD boot,if qspi is defined in env_hwconfig
1020          * disable nor flash probe.
1021          */
1022         default:
1023                 if (hwconfig_f("qspi", env_hwconfig))
1024                         is_nor_flash_available = 0;
1025                 break;
1026         }
1027         return is_nor_flash_available;
1028 }
1029 #endif
1030
1031 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1032 void *env_sf_get_env_addr(void)
1033 {
1034         return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1035 }
1036 #endif
1037 #endif