board/freescale/ls1046aqds/eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2018-2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <log.h>
   9 #include <net.h>
  10 #include <asm/io.h>
  11 #include <netdev.h>
  12 #include <fdt_support.h>
  13 #include <fm_eth.h>
  14 #include <fsl_mdio.h>
  15 #include <fsl_dtsec.h>
  16 #include <malloc.h>
  17 #include <asm/arch/fsl_serdes.h>
  18
  19 #include "../common/qixis.h"
  20 #include "../common/fman.h"
  21 #include "ls1046aqds_qixis.h"
  22
  23 #define EMI_NONE        0xFF
  24 #define EMI1_RGMII1     0
  25 #define EMI1_RGMII2     1
  26 #define EMI1_SLOT1      2
  27 #define EMI1_SLOT2      3
  28 #define EMI1_SLOT4      4
  29
  30 static const char * const mdio_names[] = {
  31         "LS1046AQDS_MDIO_RGMII1",
  32         "LS1046AQDS_MDIO_RGMII2",
  33         "LS1046AQDS_MDIO_SLOT1",
  34         "LS1046AQDS_MDIO_SLOT2",
  35         "LS1046AQDS_MDIO_SLOT4",
  36         "NULL",
  37 };
  38
  39 /* Map SerDes 1 & 2 lanes to default slot. */
  40 #ifdef CONFIG_FMAN_ENET
  41 static int mdio_mux[NUM_FM_PORTS];
  42
  43 static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
  44 #endif
  45
  46 static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
  47 {
  48         return mdio_names[muxval];
  49 }
  50
  51 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  52 {
  53         struct mii_dev *bus;
  54         const char *name;
  55
  56         if (muxval > EMI1_SLOT4)
  57                 return NULL;
  58
  59         name = ls1046aqds_mdio_name_for_muxval(muxval);
  60
  61         if (!name) {
  62                 printf("No bus for muxval %x\n", muxval);
  63                 return NULL;
  64         }
  65
  66         bus = miiphy_get_dev_by_name(name);
  67
  68         if (!bus) {
  69                 printf("No bus by name %s\n", name);
  70                 return NULL;
  71         }
  72
  73         return bus;
  74 }
  75
  76 #ifdef CONFIG_FMAN_ENET
  77 struct ls1046aqds_mdio {
  78         u8 muxval;
  79         struct mii_dev *realbus;
  80 };
  81
  82 static void ls1046aqds_mux_mdio(u8 muxval)
  83 {
  84         u8 brdcfg4;
  85
  86         if (muxval < 7) {
  87                 brdcfg4 = QIXIS_READ(brdcfg[4]);
  88                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  89                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  90                 QIXIS_WRITE(brdcfg[4], brdcfg4);
  91         }
  92 }
  93
  94 static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
  95                               int regnum)
  96 {
  97         struct ls1046aqds_mdio *priv = bus->priv;
  98
  99         ls1046aqds_mux_mdio(priv->muxval);
 100
 101         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 102 }
 103
 104 static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
 105                                int regnum, u16 value)
 106 {
 107         struct ls1046aqds_mdio *priv = bus->priv;
 108
 109         ls1046aqds_mux_mdio(priv->muxval);
 110
 111         return priv->realbus->write(priv->realbus, addr, devad,
 112                                     regnum, value);
 113 }
 114
 115 static int ls1046aqds_mdio_reset(struct mii_dev *bus)
 116 {
 117         struct ls1046aqds_mdio *priv = bus->priv;
 118
 119         return priv->realbus->reset(priv->realbus);
 120 }
 121
 122 static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
 123 {
 124         struct ls1046aqds_mdio *pmdio;
 125         struct mii_dev *bus = mdio_alloc();
 126
 127         if (!bus) {
 128                 printf("Failed to allocate ls1046aqds MDIO bus\n");
 129                 return -1;
 130         }
 131
 132         pmdio = malloc(sizeof(*pmdio));
 133         if (!pmdio) {
 134                 printf("Failed to allocate ls1046aqds private data\n");
 135                 free(bus);
 136                 return -1;
 137         }
 138
 139         bus->read = ls1046aqds_mdio_read;
 140         bus->write = ls1046aqds_mdio_write;
 141         bus->reset = ls1046aqds_mdio_reset;
 142         sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
 143
 144         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 145
 146         if (!pmdio->realbus) {
 147                 printf("No bus with name %s\n", realbusname);
 148                 free(bus);
 149                 free(pmdio);
 150                 return -1;
 151         }
 152
 153         pmdio->muxval = muxval;
 154         bus->priv = pmdio;
 155         return mdio_register(bus);
 156 }
 157
 158 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 159                               enum fm_port port, int offset)
 160 {
 161         struct fixed_link f_link;
 162         const char *phyconn;
 163
 164         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 165                 switch (port) {
 166                 case FM1_DTSEC9:
 167                         fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1");
 168                         break;
 169                 case FM1_DTSEC10:
 170                         fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2");
 171                         break;
 172                 case FM1_DTSEC5:
 173                         fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3");
 174                         break;
 175                 case FM1_DTSEC6:
 176                         fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4");
 177                         break;
 178                 case FM1_DTSEC2:
 179                         fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1");
 180                         break;
 181                 default:
 182                         break;
 183                 }
 184         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) {
 185                 /* 2.5G SGMII interface */
 186                 f_link.phy_id = cpu_to_fdt32(port);
 187                 f_link.duplex = cpu_to_fdt32(1);
 188                 f_link.link_speed = cpu_to_fdt32(1000);
 189                 f_link.pause = 0;
 190                 f_link.asym_pause = 0;
 191                 /* no PHY for 2.5G SGMII on QDS */
 192                 fdt_delprop(fdt, offset, "phy-handle");
 193                 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
 194                 fdt_setprop_string(fdt, offset, "phy-connection-type",
 195                                    "2500base-x");
 196         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
 197                 switch (port) {
 198                 case FM1_DTSEC1:
 199                         fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4");
 200                         break;
 201                 case FM1_DTSEC5:
 202                         fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2");
 203                         break;
 204                 case FM1_DTSEC6:
 205                         fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1");
 206                         break;
 207                 case FM1_DTSEC10:
 208                         fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3");
 209                         break;
 210                 default:
 211                         break;
 212                 }
 213                 fdt_delprop(fdt, offset, "phy-connection-type");
 214                 fdt_setprop_string(fdt, offset, "phy-connection-type",
 215                                    "qsgmii");
 216         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
 217                    (port == FM1_10GEC1 || port == FM1_10GEC2)) {
 218                 phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
 219                 if (is_backplane_mode(phyconn)) {
 220                         /* Backplane KR mode: skip fixups */
 221                         printf("Interface %d in backplane KR mode\n", port);
 222                 } else {
 223                         /* 10GBase-R interface */
 224                         f_link.phy_id = cpu_to_fdt32(port);
 225                         f_link.duplex = cpu_to_fdt32(1);
 226                         f_link.link_speed = cpu_to_fdt32(10000);
 227                         f_link.pause = 0;
 228                         f_link.asym_pause = 0;
 229                         /* no PHY for 10GBase-R */
 230                         fdt_delprop(fdt, offset, "phy-handle");
 231                         fdt_setprop(fdt, offset, "fixed-link", &f_link,
 232                                     sizeof(f_link));
 233                         fdt_setprop_string(fdt, offset, "phy-connection-type",
 234                                            "xgmii");
 235                 }
 236         }
 237 }
 238
 239 void fdt_fixup_board_enet(void *fdt)
 240 {
 241         int i;
 242
 243         for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 244                 switch (fm_info_get_enet_if(i)) {
 245                 case PHY_INTERFACE_MODE_SGMII:
 246                 case PHY_INTERFACE_MODE_QSGMII:
 247                         switch (mdio_mux[i]) {
 248                         case EMI1_SLOT1:
 249                                 fdt_status_okay_by_alias(fdt, "emi1-slot1");
 250                                 break;
 251                         case EMI1_SLOT2:
 252                                 fdt_status_okay_by_alias(fdt, "emi1-slot2");
 253                                 break;
 254                         case EMI1_SLOT4:
 255                                 fdt_status_okay_by_alias(fdt, "emi1-slot4");
 256                                 break;
 257                         default:
 258                                 break;
 259                         }
 260                         break;
 261                 default:
 262                         break;
 263                 }
 264         }
 265 }
 266
 267 int board_eth_init(struct bd_info *bis)
 268 {
 269         int i, idx, lane, slot, interface;
 270         struct memac_mdio_info dtsec_mdio_info;
 271         struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 272         u32 srds_s1, srds_s2;
 273         u8 brdcfg12;
 274
 275         srds_s1 = in_be32(&gur->rcwsr[4]) &
 276                         FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
 277         srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 278
 279         srds_s2 = in_be32(&gur->rcwsr[4]) &
 280                         FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
 281         srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
 282
 283         /* Initialize the mdio_mux array so we can recognize empty elements */
 284         for (i = 0; i < NUM_FM_PORTS; i++)
 285                 mdio_mux[i] = EMI_NONE;
 286
 287         dtsec_mdio_info.regs =
 288                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
 289
 290         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 291
 292         /* Register the 1G MDIO bus */
 293         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 294
 295         /* Register the muxing front-ends to the MDIO buses */
 296         ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
 297         ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
 298         ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 299         ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 300         ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 301
 302         /* Set the two on-board RGMII PHY address */
 303         fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
 304         fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
 305
 306         switch (srds_s1) {
 307         case 0x3333:
 308                 /* SGMII on slot 1, MAC 9 */
 309                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 310         case 0x1333:
 311         case 0x2333:
 312                 /* SGMII on slot 1, MAC 10 */
 313                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 314         case 0x1133:
 315         case 0x2233:
 316                 /* SGMII on slot 1, MAC 5/6 */
 317                 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 318                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 319                 break;
 320         case 0x1040:
 321         case 0x2040:
 322                 /* QSGMII on lane B, MAC 6/5/10/1 */
 323                 fm_info_set_phy_address(FM1_DTSEC6,
 324                                         QSGMII_CARD_PORT1_PHY_ADDR_S2);
 325                 fm_info_set_phy_address(FM1_DTSEC5,
 326                                         QSGMII_CARD_PORT2_PHY_ADDR_S2);
 327                 fm_info_set_phy_address(FM1_DTSEC10,
 328                                         QSGMII_CARD_PORT3_PHY_ADDR_S2);
 329                 fm_info_set_phy_address(FM1_DTSEC1,
 330                                         QSGMII_CARD_PORT4_PHY_ADDR_S2);
 331                 break;
 332         case 0x3363:
 333                 /* SGMII on slot 1, MAC 9/10 */
 334                 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
 335                 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
 336         case 0x1163:
 337         case 0x2263:
 338         case 0x2223:
 339                 /* SGMII on slot 1, MAC 6 */
 340                 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 341                 break;
 342         default:
 343                 printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
 344                        srds_s1);
 345                 break;
 346         }
 347
 348         if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
 349                 /* SGMII on slot 4, MAC 2 */
 350                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 351
 352         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 353                 idx = i - FM1_DTSEC1;
 354                 interface = fm_info_get_enet_if(i);
 355                 switch (interface) {
 356                 case PHY_INTERFACE_MODE_SGMII:
 357                 case PHY_INTERFACE_MODE_QSGMII:
 358                         if (interface == PHY_INTERFACE_MODE_SGMII) {
 359                                 if (i == FM1_DTSEC5) {
 360                                         /* route lane 2 to slot1 so to have
 361                                          * one sgmii riser card supports
 362                                          * MAC5 and MAC6.
 363                                          */
 364                                         brdcfg12 = QIXIS_READ(brdcfg[12]);
 365                                         QIXIS_WRITE(brdcfg[12],
 366                                                     brdcfg12 | 0x80);
 367                                 }
 368                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 369                                                 SGMII_FM1_DTSEC1 + idx);
 370                         } else {
 371                                 /* clear the bit 7 to route lane B on slot2. */
 372                                 brdcfg12 = QIXIS_READ(brdcfg[12]);
 373                                 QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
 374
 375                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 376                                                 QSGMII_FM1_A);
 377                                 lane_to_slot[lane] = 2;
 378                         }
 379
 380                         if (i == FM1_DTSEC2)
 381                                 lane = 5;
 382
 383                         if (lane < 0)
 384                                 break;
 385
 386                         slot = lane_to_slot[lane];
 387                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 388                               idx + 1, slot);
 389                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 390                                 fm_disable_port(i);
 391
 392                         switch (slot) {
 393                         case 1:
 394                                 mdio_mux[i] = EMI1_SLOT1;
 395                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 396                                                  mdio_mux[i]));
 397                                 break;
 398                         case 2:
 399                                 mdio_mux[i] = EMI1_SLOT2;
 400                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 401                                                  mdio_mux[i]));
 402                                 break;
 403                         case 4:
 404                                 mdio_mux[i] = EMI1_SLOT4;
 405                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 406                                                  mdio_mux[i]));
 407                                 break;
 408                         default:
 409                                 break;
 410                         }
 411                         break;
 412                 case PHY_INTERFACE_MODE_RGMII:
 413                 case PHY_INTERFACE_MODE_RGMII_TXID:
 414                 case PHY_INTERFACE_MODE_RGMII_RXID:
 415                 case PHY_INTERFACE_MODE_RGMII_ID:
 416                         if (i == FM1_DTSEC3)
 417                                 mdio_mux[i] = EMI1_RGMII1;
 418                         else if (i == FM1_DTSEC4)
 419                                 mdio_mux[i] = EMI1_RGMII2;
 420                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 421                         break;
 422                 default:
 423                         break;
 424                 }
 425         }
 426
 427         cpu_eth_init(bis);
 428
 429         return pci_eth_init(bis);
 430 }
 431 #endif /* CONFIG_FMAN_ENET */