board/freescale/ls1046aqds/ddr.c

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <fsl_ddr_sdram.h>
   9 #include <fsl_ddr_dimm_params.h>
  10 #ifdef CONFIG_FSL_DEEP_SLEEP
  11 #include <fsl_sleep.h>
  12 #endif
  13 #include "ddr.h"
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 void fsl_ddr_board_options(memctl_options_t *popts,
  18                            dimm_params_t *pdimm,
  19                            unsigned int ctrl_num)
  20 {
  21         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  22         ulong ddr_freq;
  23
  24         if (ctrl_num > 3) {
  25                 printf("Not supported controller number %d\n", ctrl_num);
  26                 return;
  27         }
  28         if (!pdimm->n_ranks)
  29                 return;
  30
  31         pbsp = udimms[0];
  32
  33         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  34          * freqency and n_banks specified in board_specific_parameters table.
  35          */
  36         ddr_freq = get_ddr_freq(0) / 1000000;
  37         while (pbsp->datarate_mhz_high) {
  38                 if (pbsp->n_ranks == pdimm->n_ranks) {
  39                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  40                                 popts->clk_adjust = pbsp->clk_adjust;
  41                                 popts->wrlvl_start = pbsp->wrlvl_start;
  42                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  43                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  44                                 goto found;
  45                         }
  46                         pbsp_highest = pbsp;
  47                 }
  48                 pbsp++;
  49         }
  50
  51         if (pbsp_highest) {
  52                 printf("Error: board specific timing not found for %lu MT/s\n",
  53                        ddr_freq);
  54                 printf("Trying to use the highest speed (%u) parameters\n",
  55                        pbsp_highest->datarate_mhz_high);
  56                 popts->clk_adjust = pbsp_highest->clk_adjust;
  57                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  58                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  59                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  60         } else {
  61                 panic("DIMM is not supported by this board");
  62         }
  63 found:
  64         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  65               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  66
  67         popts->data_bus_width = 0;      /* 64b data bus */
  68         popts->otf_burst_chop_en = 0;
  69         popts->burst_length = DDR_BL8;
  70         popts->bstopre = 0;             /* enable auto precharge */
  71
  72         popts->half_strength_driver_enable = 0;
  73         /*
  74          * Write leveling override
  75          */
  76         popts->wrlvl_override = 1;
  77         popts->wrlvl_sample = 0xf;
  78
  79         /*
  80          * Rtt and Rtt_WR override
  81          */
  82         popts->rtt_override = 0;
  83
  84         /* Enable ZQ calibration */
  85         popts->zq_en = 1;
  86
  87         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  88         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  89                           DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  90
  91         /* optimize cpo for erratum A-009942 */
  92         popts->cpo_sample = 0x70;
  93 }
  94
  95 phys_size_t initdram(int board_type)
  96 {
  97         phys_size_t dram_size;
  98
  99 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 100         return fsl_ddr_sdram_size();
 101 #else
 102         puts("Initializing DDR....using SPD\n");
 103
 104         dram_size = fsl_ddr_sdram();
 105 #endif
 106
 107 #ifdef CONFIG_FSL_DEEP_SLEEP
 108         fsl_dp_ddr_restore();
 109 #endif
 110
 111         erratum_a008850_post();
 112
 113         return dram_size;
 114 }
 115
 116 void dram_init_banksize(void)
 117 {
 118         /*
 119          * gd->arch.secure_ram tracks the location of secure memory.
 120          * It was set as if the memory starts from 0.
 121          * The address needs to add the offset of its bank.
 122          */
 123         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 124         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
 125                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
 126                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 127                 gd->bd->bi_dram[1].size = gd->ram_size -
 128                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
 129 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 130                 gd->arch.secure_ram = gd->bd->bi_dram[1].start +
 131                                  gd->arch.secure_ram -
 132                                  CONFIG_SYS_DDR_BLOCK1_SIZE;
 133                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 134 #endif
 135         } else {
 136                 gd->bd->bi_dram[0].size = gd->ram_size;
 137 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 138                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 139                                  gd->arch.secure_ram;
 140                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 141 #endif
 142         }
 143 }