1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Copyright 2021-2022 NXP
10 #include <asm/global_data.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch-fsl-layerscape/fsl_icid.h>
16 #include <fdt_support.h>
22 #include <fsl_esdhc.h>
28 #include <asm/arch/ppa.h>
30 DECLARE_GLOBAL_DATA_PTR;
33 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
37 CONFIG_SYS_NOR_CSPR_EXT,
51 CFG_SYS_NAND_CSPR_EXT,
64 CONFIG_SYS_CPLD_CSPR_EXT,
65 CONFIG_SYS_CPLD_AMASK,
68 CONFIG_SYS_CPLD_FTIM0,
69 CONFIG_SYS_CPLD_FTIM1,
70 CONFIG_SYS_CPLD_FTIM2,
76 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
80 CFG_SYS_NAND_CSPR_EXT,
93 CONFIG_SYS_NOR_CSPR_EXT,
105 CONFIG_SYS_CPLD_CSPR,
106 CONFIG_SYS_CPLD_CSPR_EXT,
107 CONFIG_SYS_CPLD_AMASK,
108 CONFIG_SYS_CPLD_CSOR,
110 CONFIG_SYS_CPLD_FTIM0,
111 CONFIG_SYS_CPLD_FTIM1,
112 CONFIG_SYS_CPLD_FTIM2,
113 CONFIG_SYS_CPLD_FTIM3
118 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
120 enum boot_src src = get_boot_src();
122 if (src == BOOT_SOURCE_IFC_NAND)
123 regs_info->regs = ifc_cfg_nand_boot;
125 regs_info->regs = ifc_cfg_nor_boot;
126 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
130 int board_early_init_f(void)
132 fsl_lsch2_early_init_f();
137 #ifndef CONFIG_SPL_BUILD
141 #ifdef CONFIG_TFABOOT
142 enum boot_src src = get_boot_src();
144 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
145 #ifndef CONFIG_SD_BOOT
146 u8 cfg_rcw_src1, cfg_rcw_src2;
151 printf("Board: LS1043ARDB, boot from ");
153 #ifdef CONFIG_TFABOOT
154 if (src == BOOT_SOURCE_SD_MMC)
159 #ifdef CONFIG_SD_BOOT
162 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
163 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
164 cpld_rev_bit(&cfg_rcw_src1);
165 cfg_rcw_src = cfg_rcw_src1;
166 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
168 if (cfg_rcw_src == 0x25)
169 printf("vBank %d\n", CPLD_READ(vbank));
170 else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118))
173 printf("Invalid setting of SW4\n");
176 #ifdef CONFIG_TFABOOT
179 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
180 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
182 puts("SERDES Reference Clocks:\n");
183 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
184 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
191 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
193 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
197 #ifdef CONFIG_FSL_IFC
198 init_final_memctl_regs();
201 #ifdef CONFIG_NXP_ESBC
202 /* In case of Secure Boot, the IBR configures the SMMU
203 * to allow only Secure transactions.
204 * SMMU must be reset in bypass mode.
205 * Set the ClientPD bit and Clear the USFCFG Bit
208 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
209 out_le32(SMMU_SCR0, val);
210 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
211 out_le32(SMMU_NSCR0, val);
214 #ifdef CONFIG_FSL_LS_PPA
218 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
225 /* invert AQR105 IRQ pins polarity */
226 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
231 int config_board_mux(void)
233 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
236 if (hwconfig("qe-hdlc")) {
237 out_be32(&scfg->rcwpmuxcr0,
238 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
239 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
240 in_be32(&scfg->rcwpmuxcr0));
242 #ifdef CONFIG_HAS_FSL_XHCI_USB
243 out_be32(&scfg->rcwpmuxcr0, 0x3333);
244 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
245 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
246 SCFG_USBPWRFAULT_USB3_SHIFT) |
247 (SCFG_USBPWRFAULT_DEDICATED <<
248 SCFG_USBPWRFAULT_USB2_SHIFT) |
249 (SCFG_USBPWRFAULT_SHARED <<
250 SCFG_USBPWRFAULT_USB1_SHIFT);
251 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
257 #if defined(CONFIG_MISC_INIT_R)
258 int misc_init_r(void)
265 void fdt_del_qe(void *blob)
269 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
271 fdt_del_node(blob, nodeoff);
275 /* Update the address of the Aquantia PHY on the MDIO bus for boards revision
276 * v7.0 and up. Also rename the PHY node to align with the address change.
278 void fdt_fixup_phy_addr(void *blob)
280 const char phy_path[] =
281 "/soc/fman@1a00000/mdio@fd000/ethernet-phy@1";
282 int ret, offset, new_addr = AQR113C_PHY_ADDR;
283 char new_name[] = "ethernet-phy@00";
285 if (CPLD_READ(pcba_ver) < 0x7)
288 offset = fdt_path_offset(blob, phy_path);
290 printf("ethernet-phy@1 node not found in the dts\n");
294 ret = fdt_setprop_u32(blob, offset, "reg", new_addr);
296 printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
301 sprintf(new_name, "ethernet-phy@%x", new_addr);
302 ret = fdt_set_name(blob, offset, new_name);
304 printf("Unable to rename node ethernet-phy@1: %s\n",
308 int ft_board_setup(void *blob, struct bd_info *bd)
310 u64 base[CONFIG_NR_DRAM_BANKS];
311 u64 size[CONFIG_NR_DRAM_BANKS];
313 /* fixup DT for the two DDR banks */
314 base[0] = gd->bd->bi_dram[0].start;
315 size[0] = gd->bd->bi_dram[0].size;
316 base[1] = gd->bd->bi_dram[1].start;
317 size[1] = gd->bd->bi_dram[1].size;
319 fdt_fixup_memory_banks(blob, base, size, 2);
320 ft_cpu_setup(blob, bd);
322 #ifdef CONFIG_SYS_DPAA_FMAN
323 #ifndef CONFIG_DM_ETH
324 fdt_fixup_fman_ethernet(blob);
326 fdt_fixup_phy_addr(blob);
329 fdt_fixup_icid(blob);
332 * qe-hdlc and usb multi-use the pins,
333 * when set hwconfig to qe-hdlc, delete usb node.
335 if (hwconfig("qe-hdlc"))
336 #ifdef CONFIG_HAS_FSL_XHCI_USB
337 fdt_del_node_and_alias(blob, "usb1");
340 * qe just support qe-uart and qe-hdlc,
341 * if qe-uart and qe-hdlc are not set in hwconfig,
344 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
350 void nand_fixup(void)
354 if (CPLD_READ(pcba_ver) < 0x7)
357 /* Change NAND Flash PGS/SPRZ configuration */
358 csor = CFG_SYS_NAND_CSOR;
359 if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
360 csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
362 if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64)
363 csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224;
365 if (IS_ENABLED(CONFIG_TFABOOT)) {
366 u8 cfg_rcw_src1, cfg_rcw_src2;
369 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
370 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
371 cpld_rev_bit(&cfg_rcw_src1);
372 cfg_rcw_src = cfg_rcw_src1;
373 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
375 if (cfg_rcw_src == 0x25)
376 set_ifc_csor(IFC_CS1, csor);
377 else if (cfg_rcw_src == 0x118)
378 set_ifc_csor(IFC_CS0, csor);
380 printf("Invalid setting\n");
382 if (IS_ENABLED(CONFIG_NAND_BOOT))
383 set_ifc_csor(IFC_CS0, csor);
385 set_ifc_csor(IFC_CS1, csor);
389 #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
390 int board_fix_fdt(void *blob)
392 /* nand driver fix up */
396 fdt_fixup_phy_addr(blob);
402 u8 flash_read8(void *addr)
404 return __raw_readb(addr + 1);
407 void flash_write16(u16 val, void *addr)
409 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
411 __raw_writew(shftval, addr);
414 u16 flash_read16(void *addr)
416 u16 val = __raw_readw(addr);
418 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);