board/freescale/ls1043ardb/ls1043ardb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  * Copyright 2021-2022 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <init.h>
  10 #include <asm/global_data.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/soc.h>
  15 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  16 #include <fdt_support.h>
  17 #include <hwconfig.h>
  18 #include <ahci.h>
  19 #include <mmc.h>
  20 #include <scsi.h>
  21 #include <fm_eth.h>
  22 #include <fsl_esdhc.h>
  23 #include <fsl_ifc.h>
  24 #include "cpld.h"
  25 #ifdef CONFIG_U_QE
  26 #include <fsl_qe.h>
  27 #endif
  28 #include <asm/arch/ppa.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #ifdef CONFIG_TFABOOT
  33 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  34         {
  35                 "nor",
  36                 CONFIG_SYS_NOR_CSPR,
  37                 CONFIG_SYS_NOR_CSPR_EXT,
  38                 CONFIG_SYS_NOR_AMASK,
  39                 CONFIG_SYS_NOR_CSOR,
  40                 {
  41                         CONFIG_SYS_NOR_FTIM0,
  42                         CONFIG_SYS_NOR_FTIM1,
  43                         CONFIG_SYS_NOR_FTIM2,
  44                         CONFIG_SYS_NOR_FTIM3
  45                 },
  46
  47         },
  48         {
  49                 "nand",
  50                 CONFIG_SYS_NAND_CSPR,
  51                 CONFIG_SYS_NAND_CSPR_EXT,
  52                 CONFIG_SYS_NAND_AMASK,
  53                 CONFIG_SYS_NAND_CSOR,
  54                 {
  55                         CONFIG_SYS_NAND_FTIM0,
  56                         CONFIG_SYS_NAND_FTIM1,
  57                         CONFIG_SYS_NAND_FTIM2,
  58                         CONFIG_SYS_NAND_FTIM3
  59                 },
  60         },
  61         {
  62                 "cpld",
  63                 CONFIG_SYS_CPLD_CSPR,
  64                 CONFIG_SYS_CPLD_CSPR_EXT,
  65                 CONFIG_SYS_CPLD_AMASK,
  66                 CONFIG_SYS_CPLD_CSOR,
  67                 {
  68                         CONFIG_SYS_CPLD_FTIM0,
  69                         CONFIG_SYS_CPLD_FTIM1,
  70                         CONFIG_SYS_CPLD_FTIM2,
  71                         CONFIG_SYS_CPLD_FTIM3
  72                 },
  73         }
  74 };
  75
  76 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  77         {
  78                 "nand",
  79                 CONFIG_SYS_NAND_CSPR,
  80                 CONFIG_SYS_NAND_CSPR_EXT,
  81                 CONFIG_SYS_NAND_AMASK,
  82                 CONFIG_SYS_NAND_CSOR,
  83                 {
  84                         CONFIG_SYS_NAND_FTIM0,
  85                         CONFIG_SYS_NAND_FTIM1,
  86                         CONFIG_SYS_NAND_FTIM2,
  87                         CONFIG_SYS_NAND_FTIM3
  88                 },
  89         },
  90         {
  91                 "nor",
  92                 CONFIG_SYS_NOR_CSPR,
  93                 CONFIG_SYS_NOR_CSPR_EXT,
  94                 CONFIG_SYS_NOR_AMASK,
  95                 CONFIG_SYS_NOR_CSOR,
  96                 {
  97                         CONFIG_SYS_NOR_FTIM0,
  98                         CONFIG_SYS_NOR_FTIM1,
  99                         CONFIG_SYS_NOR_FTIM2,
 100                         CONFIG_SYS_NOR_FTIM3
 101                 },
 102         },
 103         {
 104                 "cpld",
 105                 CONFIG_SYS_CPLD_CSPR,
 106                 CONFIG_SYS_CPLD_CSPR_EXT,
 107                 CONFIG_SYS_CPLD_AMASK,
 108                 CONFIG_SYS_CPLD_CSOR,
 109                 {
 110                         CONFIG_SYS_CPLD_FTIM0,
 111                         CONFIG_SYS_CPLD_FTIM1,
 112                         CONFIG_SYS_CPLD_FTIM2,
 113                         CONFIG_SYS_CPLD_FTIM3
 114                 },
 115         }
 116 };
 117
 118 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 119 {
 120         enum boot_src src = get_boot_src();
 121
 122         if (src == BOOT_SOURCE_IFC_NAND)
 123                 regs_info->regs = ifc_cfg_nand_boot;
 124         else
 125                 regs_info->regs = ifc_cfg_nor_boot;
 126         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 127 }
 128
 129 #endif
 130 int board_early_init_f(void)
 131 {
 132         fsl_lsch2_early_init_f();
 133
 134         return 0;
 135 }
 136
 137 #ifndef CONFIG_SPL_BUILD
 138
 139 int checkboard(void)
 140 {
 141 #ifdef CONFIG_TFABOOT
 142         enum boot_src src = get_boot_src();
 143 #endif
 144         static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
 145 #ifndef CONFIG_SD_BOOT
 146         u8 cfg_rcw_src1, cfg_rcw_src2;
 147         u16 cfg_rcw_src;
 148 #endif
 149         u8 sd1refclk_sel;
 150
 151         printf("Board: LS1043ARDB, boot from ");
 152
 153 #ifdef CONFIG_TFABOOT
 154         if (src == BOOT_SOURCE_SD_MMC)
 155                 puts("SD\n");
 156         else {
 157 #endif
 158
 159 #ifdef CONFIG_SD_BOOT
 160         puts("SD\n");
 161 #else
 162         cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
 163         cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
 164         cpld_rev_bit(&cfg_rcw_src1);
 165         cfg_rcw_src = cfg_rcw_src1;
 166         cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
 167
 168         if (cfg_rcw_src == 0x25)
 169                 printf("vBank %d\n", CPLD_READ(vbank));
 170         else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118))
 171                 puts("NAND\n");
 172         else
 173                 printf("Invalid setting of SW4\n");
 174 #endif
 175
 176 #ifdef CONFIG_TFABOOT
 177         }
 178 #endif
 179         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
 180                CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
 181
 182         puts("SERDES Reference Clocks:\n");
 183         sd1refclk_sel = CPLD_READ(sd1refclk_sel);
 184         printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
 185
 186         return 0;
 187 }
 188
 189 int board_init(void)
 190 {
 191         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 192
 193 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 194         erratum_a010315();
 195 #endif
 196
 197 #ifdef CONFIG_FSL_IFC
 198         init_final_memctl_regs();
 199 #endif
 200
 201 #ifdef CONFIG_NXP_ESBC
 202         /* In case of Secure Boot, the IBR configures the SMMU
 203          * to allow only Secure transactions.
 204          * SMMU must be reset in bypass mode.
 205          * Set the ClientPD bit and Clear the USFCFG Bit
 206          */
 207         u32 val;
 208         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 209         out_le32(SMMU_SCR0, val);
 210         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 211         out_le32(SMMU_NSCR0, val);
 212 #endif
 213
 214 #ifdef CONFIG_FSL_LS_PPA
 215         ppa_init();
 216 #endif
 217
 218 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 219         pci_init();
 220 #endif
 221
 222 #ifdef CONFIG_U_QE
 223         u_qe_init();
 224 #endif
 225         /* invert AQR105 IRQ pins polarity */
 226         out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
 227
 228         return 0;
 229 }
 230
 231 int config_board_mux(void)
 232 {
 233         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 234         u32 usb_pwrfault;
 235
 236         if (hwconfig("qe-hdlc")) {
 237                 out_be32(&scfg->rcwpmuxcr0,
 238                          (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
 239                 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
 240                        in_be32(&scfg->rcwpmuxcr0));
 241         } else {
 242 #ifdef CONFIG_HAS_FSL_XHCI_USB
 243                 out_be32(&scfg->rcwpmuxcr0, 0x3333);
 244                 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 245                 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 246                                 SCFG_USBPWRFAULT_USB3_SHIFT) |
 247                                 (SCFG_USBPWRFAULT_DEDICATED <<
 248                                 SCFG_USBPWRFAULT_USB2_SHIFT) |
 249                                 (SCFG_USBPWRFAULT_SHARED <<
 250                                  SCFG_USBPWRFAULT_USB1_SHIFT);
 251                 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 252 #endif
 253         }
 254         return 0;
 255 }
 256
 257 #if defined(CONFIG_MISC_INIT_R)
 258 int misc_init_r(void)
 259 {
 260         config_board_mux();
 261         return 0;
 262 }
 263 #endif
 264
 265 void fdt_del_qe(void *blob)
 266 {
 267         int nodeoff = 0;
 268
 269         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 270                                 "fsl,qe")) >= 0) {
 271                 fdt_del_node(blob, nodeoff);
 272         }
 273 }
 274
 275 /* Update the address of the Aquantia PHY on the MDIO bus for boards revision
 276  * v7.0 and up. Also rename the PHY node to align with the address change.
 277  */
 278 void fdt_fixup_phy_addr(void *blob)
 279 {
 280         const char phy_path[] =
 281                 "/soc/fman@1a00000/mdio@fd000/ethernet-phy@1";
 282         int ret, offset, new_addr = AQR113C_PHY_ADDR;
 283         char new_name[] = "ethernet-phy@00";
 284
 285         if (CPLD_READ(pcba_ver) < 0x7)
 286                 return;
 287
 288         offset = fdt_path_offset(blob, phy_path);
 289         if (offset < 0) {
 290                 printf("ethernet-phy@1 node not found in the dts\n");
 291                 return;
 292         }
 293
 294         ret = fdt_setprop_u32(blob, offset, "reg", new_addr);
 295         if (ret < 0) {
 296                 printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
 297                        fdt_strerror(ret));
 298                 return;
 299         }
 300
 301         sprintf(new_name, "ethernet-phy@%x", new_addr);
 302         ret = fdt_set_name(blob, offset, new_name);
 303         if (ret < 0)
 304                 printf("Unable to rename node ethernet-phy@1: %s\n",
 305                        fdt_strerror(ret));
 306 }
 307
 308 int ft_board_setup(void *blob, struct bd_info *bd)
 309 {
 310         u64 base[CONFIG_NR_DRAM_BANKS];
 311         u64 size[CONFIG_NR_DRAM_BANKS];
 312
 313         /* fixup DT for the two DDR banks */
 314         base[0] = gd->bd->bi_dram[0].start;
 315         size[0] = gd->bd->bi_dram[0].size;
 316         base[1] = gd->bd->bi_dram[1].start;
 317         size[1] = gd->bd->bi_dram[1].size;
 318
 319         fdt_fixup_memory_banks(blob, base, size, 2);
 320         ft_cpu_setup(blob, bd);
 321
 322 #ifdef CONFIG_SYS_DPAA_FMAN
 323 #ifndef CONFIG_DM_ETH
 324         fdt_fixup_fman_ethernet(blob);
 325 #endif
 326         fdt_fixup_phy_addr(blob);
 327 #endif
 328
 329         fdt_fixup_icid(blob);
 330
 331         /*
 332          * qe-hdlc and usb multi-use the pins,
 333          * when set hwconfig to qe-hdlc, delete usb node.
 334          */
 335         if (hwconfig("qe-hdlc"))
 336 #ifdef CONFIG_HAS_FSL_XHCI_USB
 337                 fdt_del_node_and_alias(blob, "usb1");
 338 #endif
 339         /*
 340          * qe just support qe-uart and qe-hdlc,
 341          * if qe-uart and qe-hdlc are not set in hwconfig,
 342          * delete qe node.
 343          */
 344         if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
 345                 fdt_del_qe(blob);
 346
 347         return 0;
 348 }
 349
 350 void nand_fixup(void)
 351 {
 352         u32 csor = 0;
 353
 354         if (CPLD_READ(pcba_ver) < 0x7)
 355                 return;
 356
 357     /* Change NAND Flash PGS/SPRZ configuration */
 358         csor = CONFIG_SYS_NAND_CSOR;
 359         if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
 360                 csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
 361
 362         if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64)
 363                 csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224;
 364
 365         if (IS_ENABLED(CONFIG_TFABOOT)) {
 366                 u8 cfg_rcw_src1, cfg_rcw_src2;
 367                 u16 cfg_rcw_src;
 368
 369                 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
 370                 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
 371                 cpld_rev_bit(&cfg_rcw_src1);
 372                 cfg_rcw_src = cfg_rcw_src1;
 373                 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
 374
 375                 if (cfg_rcw_src == 0x25)
 376                         set_ifc_csor(IFC_CS1, csor);
 377                 else if (cfg_rcw_src == 0x118)
 378                         set_ifc_csor(IFC_CS0, csor);
 379                 else
 380                         printf("Invalid setting\n");
 381         } else {
 382                 if (IS_ENABLED(CONFIG_NAND_BOOT))
 383                         set_ifc_csor(IFC_CS0, csor);
 384                 else
 385                         set_ifc_csor(IFC_CS1, csor);
 386         }
 387 }
 388
 389 #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
 390 int board_fix_fdt(void *blob)
 391 {
 392         /* nand driver fix up */
 393         nand_fixup();
 394
 395         /* fdt fix up */
 396         fdt_fixup_phy_addr(blob);
 397
 398         return 0;
 399 }
 400 #endif
 401
 402 u8 flash_read8(void *addr)
 403 {
 404         return __raw_readb(addr + 1);
 405 }
 406
 407 void flash_write16(u16 val, void *addr)
 408 {
 409         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 410
 411         __raw_writew(shftval, addr);
 412 }
 413
 414 u16 flash_read16(void *addr)
 415 {
 416         u16 val = __raw_readw(addr);
 417
 418         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 419 }
 420
 421 #endif