board/freescale/ls1043aqds/ls1043aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  * Copyright 2019-2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <clock_legacy.h>
   9 #include <i2c.h>
  10 #include <fdt_support.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/fsl_serdes.h>
  18 #include <asm/arch/ppa.h>
  19 #include <asm/arch/fdt.h>
  20 #include <asm/arch/mmu.h>
  21 #include <asm/arch/cpu.h>
  22 #include <asm/arch/soc.h>
  23 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  24 #include <ahci.h>
  25 #include <hwconfig.h>
  26 #include <mmc.h>
  27 #include <scsi.h>
  28 #include <fm_eth.h>
  29 #include <fsl_esdhc.h>
  30 #include <fsl_ifc.h>
  31 #include <spl.h>
  32 #include "../common/i2c_mux.h"
  33
  34 #include "../common/qixis.h"
  35 #include "ls1043aqds_qixis.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 enum {
  40         MUX_TYPE_GPIO,
  41 };
  42
  43 /* LS1043AQDS serdes mux */
  44 #define CFG_SD_MUX1_SLOT2       0x0 /* SLOT2 TX/RX0 */
  45 #define CFG_SD_MUX1_SLOT1       0x1 /* SLOT1 TX/RX1 */
  46 #define CFG_SD_MUX2_SLOT3       0x0 /* SLOT3 TX/RX0 */
  47 #define CFG_SD_MUX2_SLOT1       0x1 /* SLOT1 TX/RX2 */
  48 #define CFG_SD_MUX3_SLOT4       0x0 /* SLOT4 TX/RX0 */
  49 #define CFG_SD_MUX3_MUX4        0x1 /* MUX4 */
  50 #define CFG_SD_MUX4_SLOT3       0x0 /* SLOT3 TX/RX1 */
  51 #define CFG_SD_MUX4_SLOT1       0x1 /* SLOT1 TX/RX3 */
  52 #define CFG_UART_MUX_MASK       0x6
  53 #define CFG_UART_MUX_SHIFT      1
  54 #define CFG_LPUART_EN           0x1
  55
  56 #ifdef CONFIG_TFABOOT
  57 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  58         {
  59                 "nor0",
  60                 CONFIG_SYS_NOR0_CSPR,
  61                 CONFIG_SYS_NOR0_CSPR_EXT,
  62                 CONFIG_SYS_NOR_AMASK,
  63                 CONFIG_SYS_NOR_CSOR,
  64                 {
  65                         CONFIG_SYS_NOR_FTIM0,
  66                         CONFIG_SYS_NOR_FTIM1,
  67                         CONFIG_SYS_NOR_FTIM2,
  68                         CONFIG_SYS_NOR_FTIM3
  69                 },
  70
  71         },
  72         {
  73                 "nor1",
  74                 CONFIG_SYS_NOR1_CSPR,
  75                 CONFIG_SYS_NOR1_CSPR_EXT,
  76                 CONFIG_SYS_NOR_AMASK,
  77                 CONFIG_SYS_NOR_CSOR,
  78                 {
  79                         CONFIG_SYS_NOR_FTIM0,
  80                         CONFIG_SYS_NOR_FTIM1,
  81                         CONFIG_SYS_NOR_FTIM2,
  82                         CONFIG_SYS_NOR_FTIM3
  83                 },
  84         },
  85         {
  86                 "nand",
  87                 CONFIG_SYS_NAND_CSPR,
  88                 CONFIG_SYS_NAND_CSPR_EXT,
  89                 CONFIG_SYS_NAND_AMASK,
  90                 CONFIG_SYS_NAND_CSOR,
  91                 {
  92                         CONFIG_SYS_NAND_FTIM0,
  93                         CONFIG_SYS_NAND_FTIM1,
  94                         CONFIG_SYS_NAND_FTIM2,
  95                         CONFIG_SYS_NAND_FTIM3
  96                 },
  97         },
  98         {
  99                 "fpga",
 100                 CONFIG_SYS_FPGA_CSPR,
 101                 CONFIG_SYS_FPGA_CSPR_EXT,
 102                 CONFIG_SYS_FPGA_AMASK,
 103                 CONFIG_SYS_FPGA_CSOR,
 104                 {
 105                         CONFIG_SYS_FPGA_FTIM0,
 106                         CONFIG_SYS_FPGA_FTIM1,
 107                         CONFIG_SYS_FPGA_FTIM2,
 108                         CONFIG_SYS_FPGA_FTIM3
 109                 },
 110         }
 111 };
 112
 113 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 114         {
 115                 "nand",
 116                 CONFIG_SYS_NAND_CSPR,
 117                 CONFIG_SYS_NAND_CSPR_EXT,
 118                 CONFIG_SYS_NAND_AMASK,
 119                 CONFIG_SYS_NAND_CSOR,
 120                 {
 121                         CONFIG_SYS_NAND_FTIM0,
 122                         CONFIG_SYS_NAND_FTIM1,
 123                         CONFIG_SYS_NAND_FTIM2,
 124                         CONFIG_SYS_NAND_FTIM3
 125                 },
 126         },
 127         {
 128                 "nor0",
 129                 CONFIG_SYS_NOR0_CSPR,
 130                 CONFIG_SYS_NOR0_CSPR_EXT,
 131                 CONFIG_SYS_NOR_AMASK,
 132                 CONFIG_SYS_NOR_CSOR,
 133                 {
 134                         CONFIG_SYS_NOR_FTIM0,
 135                         CONFIG_SYS_NOR_FTIM1,
 136                         CONFIG_SYS_NOR_FTIM2,
 137                         CONFIG_SYS_NOR_FTIM3
 138                 },
 139         },
 140         {
 141                 "nor1",
 142                 CONFIG_SYS_NOR1_CSPR,
 143                 CONFIG_SYS_NOR1_CSPR_EXT,
 144                 CONFIG_SYS_NOR_AMASK,
 145                 CONFIG_SYS_NOR_CSOR,
 146                 {
 147                         CONFIG_SYS_NOR_FTIM0,
 148                         CONFIG_SYS_NOR_FTIM1,
 149                         CONFIG_SYS_NOR_FTIM2,
 150                         CONFIG_SYS_NOR_FTIM3
 151                 },
 152         },
 153         {
 154                 "fpga",
 155                 CONFIG_SYS_FPGA_CSPR,
 156                 CONFIG_SYS_FPGA_CSPR_EXT,
 157                 CONFIG_SYS_FPGA_AMASK,
 158                 CONFIG_SYS_FPGA_CSOR,
 159                 {
 160                         CONFIG_SYS_FPGA_FTIM0,
 161                         CONFIG_SYS_FPGA_FTIM1,
 162                         CONFIG_SYS_FPGA_FTIM2,
 163                         CONFIG_SYS_FPGA_FTIM3
 164                 },
 165         }
 166 };
 167
 168 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 169 {
 170         enum boot_src src = get_boot_src();
 171
 172         if (src == BOOT_SOURCE_IFC_NAND)
 173                 regs_info->regs = ifc_cfg_nand_boot;
 174         else
 175                 regs_info->regs = ifc_cfg_nor_boot;
 176         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 177 }
 178 #endif
 179
 180 int checkboard(void)
 181 {
 182 #ifdef CONFIG_TFABOOT
 183         enum boot_src src = get_boot_src();
 184 #endif
 185         char buf[64];
 186 #ifndef CONFIG_SD_BOOT
 187         u8 sw;
 188 #endif
 189
 190         puts("Board: LS1043AQDS, boot from ");
 191
 192 #ifdef CONFIG_TFABOOT
 193         if (src == BOOT_SOURCE_SD_MMC)
 194                 puts("SD\n");
 195         else {
 196 #endif
 197
 198 #ifdef CONFIG_SD_BOOT
 199         puts("SD\n");
 200 #else
 201         sw = QIXIS_READ(brdcfg[0]);
 202         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 203
 204         if (sw < 0x8)
 205                 printf("vBank: %d\n", sw);
 206         else if (sw == 0x8)
 207                 puts("PromJet\n");
 208         else if (sw == 0x9)
 209                 puts("NAND\n");
 210         else if (sw == 0xF)
 211                 printf("QSPI\n");
 212         else
 213                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 214 #endif
 215
 216 #ifdef CONFIG_TFABOOT
 217         }
 218 #endif
 219         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
 220                QIXIS_READ(id), QIXIS_READ(arch));
 221
 222         printf("FPGA:  v%d (%s), build %d\n",
 223                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 224                (int)qixis_read_minor());
 225
 226         return 0;
 227 }
 228
 229 bool if_board_diff_clk(void)
 230 {
 231         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 232
 233         return diff_conf & 0x40;
 234 }
 235
 236 unsigned long get_board_sys_clk(void)
 237 {
 238         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 239
 240         switch (sysclk_conf & 0x0f) {
 241         case QIXIS_SYSCLK_64:
 242                 return 64000000;
 243         case QIXIS_SYSCLK_83:
 244                 return 83333333;
 245         case QIXIS_SYSCLK_100:
 246                 return 100000000;
 247         case QIXIS_SYSCLK_125:
 248                 return 125000000;
 249         case QIXIS_SYSCLK_133:
 250                 return 133333333;
 251         case QIXIS_SYSCLK_150:
 252                 return 150000000;
 253         case QIXIS_SYSCLK_160:
 254                 return 160000000;
 255         case QIXIS_SYSCLK_166:
 256                 return 166666666;
 257         }
 258
 259         return 66666666;
 260 }
 261
 262 unsigned long get_board_ddr_clk(void)
 263 {
 264         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 265
 266         if (if_board_diff_clk())
 267                 return get_board_sys_clk();
 268         switch ((ddrclk_conf & 0x30) >> 4) {
 269         case QIXIS_DDRCLK_100:
 270                 return 100000000;
 271         case QIXIS_DDRCLK_125:
 272                 return 125000000;
 273         case QIXIS_DDRCLK_133:
 274                 return 133333333;
 275         }
 276
 277         return 66666666;
 278 }
 279
 280 int dram_init(void)
 281 {
 282         /*
 283          * When resuming from deep sleep, the I2C channel may not be
 284          * in the default channel. So, switch to the default channel
 285          * before accessing DDR SPD.
 286          *
 287          * PCA9547 mount on I2C1 bus
 288          */
 289         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 290         fsl_initdram();
 291 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
 292         defined(CONFIG_SPL_BUILD)
 293         /* This will break-before-make MMU for DDR */
 294         update_early_mmu_table();
 295 #endif
 296
 297         return 0;
 298 }
 299
 300 int i2c_multiplexer_select_vid_channel(u8 channel)
 301 {
 302         return select_i2c_ch_pca9547(channel, 0);
 303 }
 304
 305 void board_retimer_init(void)
 306 {
 307         u8 reg;
 308         int bus_num = 0;
 309
 310         /* Retimer is connected to I2C1_CH7_CH5 */
 311         select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
 312         reg = I2C_MUX_CH5;
 313 #if CONFIG_IS_ENABLED(DM_I2C)
 314         struct udevice *dev;
 315         int ret;
 316
 317         ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
 318                                       1, &dev);
 319         if (ret) {
 320                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 321                        bus_num);
 322                 return;
 323         }
 324         dm_i2c_write(dev, 0, &reg, 1);
 325
 326         /* Access to Control/Shared register */
 327         ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
 328                                       1, &dev);
 329         if (ret) {
 330                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 331                        bus_num);
 332                 return;
 333         }
 334
 335         reg = 0x0;
 336         dm_i2c_write(dev, 0xff, &reg, 1);
 337
 338         /* Read device revision and ID */
 339         dm_i2c_read(dev, 1, &reg, 1);
 340         debug("Retimer version id = 0x%x\n", reg);
 341
 342         /* Enable Broadcast. All writes target all channel register sets */
 343         reg = 0x0c;
 344         dm_i2c_write(dev, 0xff, &reg, 1);
 345
 346         /* Reset Channel Registers */
 347         dm_i2c_read(dev, 0, &reg, 1);
 348         reg |= 0x4;
 349         dm_i2c_write(dev, 0, &reg, 1);
 350
 351         /* Enable override divider select and Enable Override Output Mux */
 352         dm_i2c_read(dev, 9, &reg, 1);
 353         reg |= 0x24;
 354         dm_i2c_write(dev, 9, &reg, 1);
 355
 356         /* Select VCO Divider to full rate (000) */
 357         dm_i2c_read(dev, 0x18, &reg, 1);
 358         reg &= 0x8f;
 359         dm_i2c_write(dev, 0x18, &reg, 1);
 360
 361         /* Selects active PFD MUX Input as Re-timed Data (001) */
 362         dm_i2c_read(dev, 0x1e, &reg, 1);
 363         reg &= 0x3f;
 364         reg |= 0x20;
 365         dm_i2c_write(dev, 0x1e, &reg, 1);
 366
 367         /* Set data rate as 10.3125 Gbps */
 368         reg = 0x0;
 369         dm_i2c_write(dev, 0x60, &reg, 1);
 370         reg = 0xb2;
 371         dm_i2c_write(dev, 0x61, &reg, 1);
 372         reg = 0x90;
 373         dm_i2c_write(dev, 0x62, &reg, 1);
 374         reg = 0xb3;
 375         dm_i2c_write(dev, 0x63, &reg, 1);
 376         reg = 0xcd;
 377         dm_i2c_write(dev, 0x64, &reg, 1);
 378 #else
 379         i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 380
 381         /* Access to Control/Shared register */
 382         reg = 0x0;
 383         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 384
 385         /* Read device revision and ID */
 386         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 387         debug("Retimer version id = 0x%x\n", reg);
 388
 389         /* Enable Broadcast. All writes target all channel register sets */
 390         reg = 0x0c;
 391         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 392
 393         /* Reset Channel Registers */
 394         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 395         reg |= 0x4;
 396         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 397
 398         /* Enable override divider select and Enable Override Output Mux */
 399         i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 400         reg |= 0x24;
 401         i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
 402
 403         /* Select VCO Divider to full rate (000) */
 404         i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 405         reg &= 0x8f;
 406         i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
 407
 408         /* Selects active PFD MUX Input as Re-timed Data (001) */
 409         i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 410         reg &= 0x3f;
 411         reg |= 0x20;
 412         i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
 413
 414         /* Set data rate as 10.3125 Gbps */
 415         reg = 0x0;
 416         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 417         reg = 0xb2;
 418         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 419         reg = 0x90;
 420         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 421         reg = 0xb3;
 422         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 423         reg = 0xcd;
 424         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 425 #endif
 426
 427         /* Return the default channel */
 428         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
 429 }
 430
 431 int board_early_init_f(void)
 432 {
 433         u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
 434 #ifdef CONFIG_HAS_FSL_XHCI_USB
 435         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 436         u32 usb_pwrfault;
 437 #endif
 438 #ifdef CONFIG_LPUART
 439         u8 uart;
 440 #endif
 441
 442         /*
 443          * Enable secure system counter for timer
 444          */
 445         out_le32(cntcr, 0x1);
 446
 447 #if defined(CONFIG_SYS_I2C_EARLY_INIT)
 448         i2c_early_init_f();
 449 #endif
 450         fsl_lsch2_early_init_f();
 451
 452 #ifdef CONFIG_HAS_FSL_XHCI_USB
 453         out_be32(&scfg->rcwpmuxcr0, 0x3333);
 454         out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 455         usb_pwrfault =
 456                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
 457                 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 458                 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 459         out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 460 #endif
 461
 462 #ifdef CONFIG_LPUART
 463         /* We use lpuart0 as system console */
 464         uart = QIXIS_READ(brdcfg[14]);
 465         uart &= ~CFG_UART_MUX_MASK;
 466         uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
 467         QIXIS_WRITE(brdcfg[14], uart);
 468 #endif
 469
 470         return 0;
 471 }
 472
 473 #ifdef CONFIG_FSL_DEEP_SLEEP
 474 /* determine if it is a warm boot */
 475 bool is_warm_boot(void)
 476 {
 477 #define DCFG_CCSR_CRSTSR_WDRFR  (1 << 3)
 478         struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
 479
 480         if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
 481                 return 1;
 482
 483         return 0;
 484 }
 485 #endif
 486
 487 int config_board_mux(int ctrl_type)
 488 {
 489         u8 reg14;
 490
 491         reg14 = QIXIS_READ(brdcfg[14]);
 492
 493         switch (ctrl_type) {
 494         case MUX_TYPE_GPIO:
 495                 reg14 = (reg14 & (~0x30)) | 0x20;
 496                 break;
 497         default:
 498                 puts("Unsupported mux interface type\n");
 499                 return -1;
 500         }
 501
 502         QIXIS_WRITE(brdcfg[14], reg14);
 503
 504         return 0;
 505 }
 506
 507 int config_serdes_mux(void)
 508 {
 509         return 0;
 510 }
 511
 512
 513 #ifdef CONFIG_MISC_INIT_R
 514 int misc_init_r(void)
 515 {
 516         if (hwconfig("gpio"))
 517                 config_board_mux(MUX_TYPE_GPIO);
 518
 519         return 0;
 520 }
 521 #endif
 522
 523 int board_init(void)
 524 {
 525 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 526         erratum_a010315();
 527 #endif
 528
 529         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 530         board_retimer_init();
 531
 532 #ifdef CFG_SYS_FSL_SERDES
 533         config_serdes_mux();
 534 #endif
 535
 536 #ifdef CONFIG_FSL_LS_PPA
 537         ppa_init();
 538 #endif
 539
 540         return 0;
 541 }
 542
 543 #ifdef CONFIG_OF_BOARD_SETUP
 544 int ft_board_setup(void *blob, struct bd_info *bd)
 545 {
 546         u64 base[CONFIG_NR_DRAM_BANKS];
 547         u64 size[CONFIG_NR_DRAM_BANKS];
 548         u8 reg;
 549
 550         /* fixup DT for the two DDR banks */
 551         base[0] = gd->bd->bi_dram[0].start;
 552         size[0] = gd->bd->bi_dram[0].size;
 553         base[1] = gd->bd->bi_dram[1].start;
 554         size[1] = gd->bd->bi_dram[1].size;
 555
 556         fdt_fixup_memory_banks(blob, base, size, 2);
 557         ft_cpu_setup(blob, bd);
 558
 559 #ifdef CONFIG_FMAN_ENET
 560         fdt_fixup_board_enet(blob);
 561 #endif
 562
 563         fdt_fixup_icid(blob);
 564
 565         reg = QIXIS_READ(brdcfg[0]);
 566         reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 567
 568         /* Disable IFC if QSPI is enabled */
 569         if (reg == 0xF)
 570                 do_fixup_by_compat(blob, "fsl,ifc",
 571                                    "status", "disabled", 8 + 1, 1);
 572
 573         return 0;
 574 }
 575 #endif
 576
 577 u8 flash_read8(void *addr)
 578 {
 579         return __raw_readb(addr + 1);
 580 }
 581
 582 void flash_write16(u16 val, void *addr)
 583 {
 584         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 585
 586         __raw_writew(shftval, addr);
 587 }
 588
 589 u16 flash_read16(void *addr)
 590 {
 591         u16 val = __raw_readw(addr);
 592
 593         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 594 }
 595
 596 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 597 void *env_sf_get_env_addr(void)
 598 {
 599         return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
 600 }
 601 #endif