board/freescale/ls1021atwr/ls1021atwr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019, 2021-2022 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <clock_legacy.h>
   9 #include <command.h>
  10 #include <fdt_support.h>
  11 #include <i2c.h>
  12 #include <init.h>
  13 #include <net.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/immap_ls102xa.h>
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/fsl_serdes.h>
  19 #include <asm/arch/ls102xa_devdis.h>
  20 #include <asm/arch/ls102xa_soc.h>
  21 #include <hwconfig.h>
  22 #include <mmc.h>
  23 #include <fsl_csu.h>
  24 #include <fsl_ifc.h>
  25 #include <fsl_immap.h>
  26 #include <netdev.h>
  27 #include <fsl_mdio.h>
  28 #include <tsec.h>
  29 #include <fsl_devdis.h>
  30 #include <spl.h>
  31 #include <linux/delay.h>
  32 #include "../common/sleep.h"
  33 #ifdef CONFIG_U_QE
  34 #include <fsl_qe.h>
  35 #endif
  36 #include <fsl_validate.h>
  37 #include <dm/uclass.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #define VERSION_MASK            0x00FF
  42 #define BANK_MASK               0x0001
  43 #define CFG_RESET               0x1
  44 #define INIT_RESET              0x1
  45
  46 #define CPLD_SET_MUX_SERDES     0x20
  47 #define CPLD_SET_BOOT_BANK      0x40
  48
  49 #define BOOT_FROM_UPPER_BANK    0x0
  50 #define BOOT_FROM_LOWER_BANK    0x1
  51
  52 #define LANEB_SATA              (0x01)
  53 #define LANEB_SGMII1            (0x02)
  54 #define LANEC_SGMII1            (0x04)
  55 #define LANEC_PCIEX1            (0x08)
  56 #define LANED_PCIEX2            (0x10)
  57 #define LANED_SGMII2            (0x20)
  58
  59 #define MASK_LANE_B             0x1
  60 #define MASK_LANE_C             0x2
  61 #define MASK_LANE_D             0x4
  62 #define MASK_SGMII              0x8
  63
  64 #define KEEP_STATUS             0x0
  65 #define NEED_RESET              0x1
  66
  67 #define SOFT_MUX_ON_I2C3_IFC    0x2
  68 #define SOFT_MUX_ON_CAN3_USB2   0x8
  69 #define SOFT_MUX_ON_QE_LCD      0x10
  70
  71 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  72 #define PIN_I2C3_IFC_MUX_IFC    0x1
  73 #define PIN_CAN3_USB2_MUX_USB2  0x0
  74 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  75 #define PIN_QE_LCD_MUX_LCD      0x0
  76 #define PIN_QE_LCD_MUX_QE       0x1
  77
  78 struct cpld_data {
  79         u8 cpld_ver;            /* cpld revision */
  80         u8 cpld_ver_sub;        /* cpld sub revision */
  81         u8 pcba_ver;            /* pcb revision number */
  82         u8 system_rst;          /* reset system by cpld */
  83         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  84         u8 cfg_rcw_src1;        /* Reset config word 1 */
  85         u8 cfg_rcw_src2;        /* Reset config word 2 */
  86         u8 vbank;               /* Flash bank selection Control */
  87         u8 gpio;                /* GPIO for TWR-ELEV */
  88         u8 i2c3_ifc_mux;
  89         u8 mux_spi2;
  90         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  91         u8 qe_lcd_mux;          /* QE and LCD Selection */
  92         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  93         u8 global_rst;          /* reset with init CPLD reg to default */
  94         u8 rev1;                /* Reserved */
  95         u8 rev2;                /* Reserved */
  96 };
  97
  98 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  99 static void cpld_show(void)
 100 {
 101         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 102
 103         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
 104                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
 105                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 106                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 107                in_8(&cpld_data->vbank) & BANK_MASK);
 108
 109 #ifdef DEBUG
 110         printf("soft_mux_on =%x\n",
 111                in_8(&cpld_data->soft_mux_on));
 112         printf("cfg_rcw_src1 =%x\n",
 113                in_8(&cpld_data->cfg_rcw_src1));
 114         printf("cfg_rcw_src2 =%x\n",
 115                in_8(&cpld_data->cfg_rcw_src2));
 116         printf("vbank =%x\n",
 117                in_8(&cpld_data->vbank));
 118         printf("gpio =%x\n",
 119                in_8(&cpld_data->gpio));
 120         printf("i2c3_ifc_mux =%x\n",
 121                in_8(&cpld_data->i2c3_ifc_mux));
 122         printf("mux_spi2 =%x\n",
 123                in_8(&cpld_data->mux_spi2));
 124         printf("can3_usb2_mux =%x\n",
 125                in_8(&cpld_data->can3_usb2_mux));
 126         printf("qe_lcd_mux =%x\n",
 127                in_8(&cpld_data->qe_lcd_mux));
 128         printf("serdes_mux =%x\n",
 129                in_8(&cpld_data->serdes_mux));
 130 #endif
 131 }
 132 #endif
 133
 134 int checkboard(void)
 135 {
 136         puts("Board: LS1021ATWR\n");
 137 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 138         cpld_show();
 139 #endif
 140
 141         return 0;
 142 }
 143
 144 void ddrmc_init(void)
 145 {
 146         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 147         u32 temp_sdram_cfg, tmp;
 148
 149         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 150
 151         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 152         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 153
 154         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 155         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 156         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 157         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 158         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 159         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 160
 161 #ifdef CONFIG_DEEP_SLEEP
 162         if (is_warm_boot()) {
 163                 out_be32(&ddr->sdram_cfg_2,
 164                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 165                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 166                 out_be32(&ddr->init_ext_addr, (1 << 31));
 167
 168                 /* DRAM VRef will not be trained */
 169                 out_be32(&ddr->ddr_cdr2,
 170                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 171         } else
 172 #endif
 173         {
 174                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 175                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 176         }
 177
 178         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 179         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 180
 181         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 182
 183         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 184
 185         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 186         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 187
 188         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 189
 190         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 191         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 192
 193         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 194
 195         /* DDR erratum A-009942 */
 196         tmp = in_be32(&ddr->debug[28]);
 197         out_be32(&ddr->debug[28], tmp | 0x0070006f);
 198
 199         udelay(1);
 200
 201 #ifdef CONFIG_DEEP_SLEEP
 202         if (is_warm_boot()) {
 203                 /* enter self-refresh */
 204                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 205                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 206                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 207
 208                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 209         } else
 210 #endif
 211                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 212
 213         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 214
 215 #ifdef CONFIG_DEEP_SLEEP
 216         if (is_warm_boot()) {
 217                 /* exit self-refresh */
 218                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 219                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 220                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 221         }
 222 #endif
 223 }
 224
 225 int dram_init(void)
 226 {
 227 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 228         ddrmc_init();
 229 #endif
 230
 231         erratum_a008850_post();
 232
 233         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 234
 235 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 236         fsl_dp_resume();
 237 #endif
 238
 239         return 0;
 240 }
 241
 242 int board_eth_init(struct bd_info *bis)
 243 {
 244         return pci_eth_init(bis);
 245 }
 246
 247 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 248 static void convert_serdes_mux(int type, int need_reset)
 249 {
 250         char current_serdes;
 251         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 252
 253         current_serdes = cpld_data->serdes_mux;
 254
 255         switch (type) {
 256         case LANEB_SATA:
 257                 current_serdes &= ~MASK_LANE_B;
 258                 break;
 259         case LANEB_SGMII1:
 260                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 261                 break;
 262         case LANEC_SGMII1:
 263                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 264                 break;
 265         case LANED_SGMII2:
 266                 current_serdes |= MASK_LANE_D;
 267                 break;
 268         case LANEC_PCIEX1:
 269                 current_serdes |= MASK_LANE_C;
 270                 break;
 271         case (LANED_PCIEX2 | LANEC_PCIEX1):
 272                 current_serdes |= MASK_LANE_C;
 273                 current_serdes &= ~MASK_LANE_D;
 274                 break;
 275         default:
 276                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 277                 return;
 278         }
 279
 280         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 281         cpld_data->serdes_mux = current_serdes;
 282
 283         if (need_reset == 1) {
 284                 printf("Reset board to enable configuration\n");
 285                 cpld_data->system_rst = CFG_RESET;
 286         }
 287 }
 288
 289 int config_serdes_mux(void)
 290 {
 291         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 292         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 293
 294         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 295         switch (protocol) {
 296         case 0x10:
 297                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 298                 convert_serdes_mux(LANED_PCIEX2 |
 299                                 LANEC_PCIEX1, KEEP_STATUS);
 300                 break;
 301         case 0x20:
 302                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 303                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 304                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 305                 break;
 306         case 0x30:
 307                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 308                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 309                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 310                 break;
 311         case 0x70:
 312                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 313                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 314                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 315                 break;
 316         }
 317
 318         return 0;
 319 }
 320 #endif
 321
 322 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 323 int config_board_mux(void)
 324 {
 325         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 326         int conflict_flag;
 327
 328         conflict_flag = 0;
 329         if (hwconfig("i2c3")) {
 330                 conflict_flag++;
 331                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 332                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 333         }
 334
 335         if (hwconfig("ifc")) {
 336                 conflict_flag++;
 337                 /* some signals can not enable simultaneous*/
 338                 if (conflict_flag > 1)
 339                         goto conflict;
 340                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 341                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 342         }
 343
 344         conflict_flag = 0;
 345         if (hwconfig("usb2")) {
 346                 conflict_flag++;
 347                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 348                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 349         }
 350
 351         if (hwconfig("can3")) {
 352                 conflict_flag++;
 353                 /* some signals can not enable simultaneous*/
 354                 if (conflict_flag > 1)
 355                         goto conflict;
 356                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 357                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 358         }
 359
 360         conflict_flag = 0;
 361         if (hwconfig("lcd")) {
 362                 conflict_flag++;
 363                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 364                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 365         }
 366
 367         if (hwconfig("qe")) {
 368                 conflict_flag++;
 369                 /* some signals can not enable simultaneous*/
 370                 if (conflict_flag > 1)
 371                         goto conflict;
 372                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 373                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 374         }
 375
 376         return 0;
 377
 378 conflict:
 379         printf("WARNING: pin conflict! MUX setting may failed!\n");
 380         return 0;
 381 }
 382 #endif
 383
 384 int board_early_init_f(void)
 385 {
 386         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 387
 388 #ifdef CONFIG_TSEC_ENET
 389         /* clear BD & FR bits for BE BD's and frame data */
 390         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 391         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 392 #endif
 393
 394 #ifdef CONFIG_FSL_IFC
 395         init_early_memctl_regs();
 396 #endif
 397
 398         arch_soc_init();
 399
 400 #if defined(CONFIG_DEEP_SLEEP)
 401         if (is_warm_boot()) {
 402                 timer_init();
 403                 dram_init();
 404         }
 405 #endif
 406
 407         return 0;
 408 }
 409
 410 #ifdef CONFIG_SPL_BUILD
 411 void board_init_f(ulong dummy)
 412 {
 413         void (*second_uboot)(void);
 414
 415         /* Clear the BSS */
 416         memset(__bss_start, 0, __bss_end - __bss_start);
 417
 418         get_clocks();
 419
 420 #if defined(CONFIG_DEEP_SLEEP)
 421         if (is_warm_boot())
 422                 fsl_dp_disable_console();
 423 #endif
 424
 425         preloader_console_init();
 426
 427         timer_init();
 428         dram_init();
 429
 430         /* Allow OCRAM access permission as R/W */
 431 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 432         enable_layerscape_ns_access();
 433 #endif
 434
 435         /*
 436          * if it is woken up from deep sleep, then jump to second
 437          * stage uboot and continue executing without recopying
 438          * it from SD since it has already been reserved in memeory
 439          * in last boot.
 440          */
 441         if (is_warm_boot()) {
 442                 second_uboot = (void (*)(void))CONFIG_TEXT_BASE;
 443                 second_uboot();
 444         }
 445
 446         board_init_r(NULL, 0);
 447 }
 448 #endif
 449
 450 #ifdef CONFIG_DEEP_SLEEP
 451 /* program the regulator (MC34VR500) to support deep sleep */
 452 void ls1twr_program_regulator(void)
 453 {
 454         u8 i2c_device_id;
 455
 456 #define LS1TWR_I2C_BUS_MC34VR500        1
 457 #define MC34VR500_ADDR                  0x8
 458 #define MC34VR500_DEVICEID              0x4
 459 #define MC34VR500_DEVICEID_MASK         0x0f
 460 #if CONFIG_IS_ENABLED(DM_I2C)
 461         struct udevice *dev;
 462         int ret;
 463
 464         ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
 465                                       1, &dev);
 466         if (ret) {
 467                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 468                        LS1TWR_I2C_BUS_MC34VR500);
 469                 return;
 470         }
 471         i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
 472                                         MC34VR500_DEVICEID_MASK;
 473         if (i2c_device_id != MC34VR500_DEVICEID) {
 474                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 475                 return;
 476         }
 477
 478         dm_i2c_reg_write(dev, 0x31, 0x4);
 479         dm_i2c_reg_write(dev, 0x4d, 0x4);
 480         dm_i2c_reg_write(dev, 0x6d, 0x38);
 481         dm_i2c_reg_write(dev, 0x6f, 0x37);
 482         dm_i2c_reg_write(dev, 0x71, 0x30);
 483 #else
 484         unsigned int i2c_bus;
 485         i2c_bus = i2c_get_bus_num();
 486         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 487         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
 488                                         MC34VR500_DEVICEID_MASK;
 489         if (i2c_device_id != MC34VR500_DEVICEID) {
 490                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 491                 return;
 492         }
 493
 494         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
 495         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
 496         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
 497         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
 498         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 499
 500         i2c_set_bus_num(i2c_bus);
 501 #endif
 502 }
 503 #endif
 504
 505 int board_init(void)
 506 {
 507 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 508         erratum_a010315();
 509 #endif
 510
 511 #ifndef CONFIG_SYS_FSL_NO_SERDES
 512         fsl_serdes_init();
 513 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 514         config_serdes_mux();
 515 #endif
 516 #endif
 517
 518         ls102xa_smmu_stream_id_init();
 519
 520 #ifdef CONFIG_U_QE
 521         u_qe_init();
 522 #endif
 523
 524 #ifdef CONFIG_DEEP_SLEEP
 525         ls1twr_program_regulator();
 526 #endif
 527         return 0;
 528 }
 529
 530 #if defined(CONFIG_SPL_BUILD)
 531 void spl_board_init(void)
 532 {
 533         if (IS_ENABLED(CONFIG_FSL_CAAM)) {
 534                 struct udevice *dev;
 535                 int ret;
 536
 537                 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
 538                 if (ret)
 539                         printf("Failed to initialize caam_jr: %d\n", ret);
 540         }
 541
 542         ls102xa_smmu_stream_id_init();
 543 }
 544 #endif
 545
 546 #ifdef CONFIG_BOARD_LATE_INIT
 547 int board_late_init(void)
 548 {
 549 #ifdef CONFIG_CHAIN_OF_TRUST
 550         fsl_setenv_chain_of_trust();
 551 #endif
 552
 553         return 0;
 554 }
 555 #endif
 556
 557 #if defined(CONFIG_MISC_INIT_R)
 558 int misc_init_r(void)
 559 {
 560 #ifdef CONFIG_FSL_DEVICE_DISABLE
 561         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 562 #endif
 563 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 564         config_board_mux();
 565 #endif
 566         return 0;
 567 }
 568 #endif
 569
 570 #if defined(CONFIG_DEEP_SLEEP)
 571 void board_sleep_prepare(void)
 572 {
 573 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 574         enable_layerscape_ns_access();
 575 #endif
 576 }
 577 #endif
 578
 579 int ft_board_setup(void *blob, struct bd_info *bd)
 580 {
 581         ft_cpu_setup(blob, bd);
 582
 583 #ifdef CONFIG_PCI
 584         ft_pci_setup(blob, bd);
 585 #endif
 586
 587         return 0;
 588 }
 589
 590 u8 flash_read8(void *addr)
 591 {
 592         return __raw_readb(addr + 1);
 593 }
 594
 595 void flash_write16(u16 val, void *addr)
 596 {
 597         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 598
 599         __raw_writew(shftval, addr);
 600 }
 601
 602 u16 flash_read16(void *addr)
 603 {
 604         u16 val = __raw_readw(addr);
 605
 606         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 607 }
 608
 609 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
 610         && !defined(CONFIG_SPL_BUILD)
 611 static void convert_flash_bank(char bank)
 612 {
 613         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 614
 615         printf("Now switch to boot from flash bank %d.\n", bank);
 616         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 617         cpld_data->vbank = bank;
 618
 619         printf("Reset board to enable configuration.\n");
 620         cpld_data->system_rst = CFG_RESET;
 621 }
 622
 623 static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 624                           char *const argv[])
 625 {
 626         if (argc != 2)
 627                 return CMD_RET_USAGE;
 628         if (strcmp(argv[1], "0") == 0)
 629                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 630         else if (strcmp(argv[1], "1") == 0)
 631                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 632         else
 633                 return CMD_RET_USAGE;
 634
 635         return 0;
 636 }
 637
 638 U_BOOT_CMD(
 639         boot_bank, 2, 0, flash_bank_cmd,
 640         "Flash bank Selection Control",
 641         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 642 );
 643
 644 static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 645                           char *const argv[])
 646 {
 647         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 648
 649         if (argc > 2)
 650                 return CMD_RET_USAGE;
 651         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 652                 cpld_data->system_rst = CFG_RESET;
 653         else if (strcmp(argv[1], "init") == 0)
 654                 cpld_data->global_rst = INIT_RESET;
 655         else
 656                 return CMD_RET_USAGE;
 657
 658         return 0;
 659 }
 660
 661 U_BOOT_CMD(
 662         cpld_reset, 2, 0, cpld_reset_cmd,
 663         "Reset via CPLD",
 664         "conf\n"
 665         "       -reset with current CPLD configuration\n"
 666         "init\n"
 667         "       -reset and initial CPLD configuration with default value"
 668
 669 );
 670
 671 static void print_serdes_mux(void)
 672 {
 673         char current_serdes;
 674         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 675
 676         current_serdes = cpld_data->serdes_mux;
 677
 678         printf("Serdes Lane B: ");
 679         if ((current_serdes & MASK_LANE_B) == 0)
 680                 printf("SATA,\n");
 681         else
 682                 printf("SGMII 1,\n");
 683
 684         printf("Serdes Lane C: ");
 685         if ((current_serdes & MASK_LANE_C) == 0)
 686                 printf("SGMII 1,\n");
 687         else
 688                 printf("PCIe,\n");
 689
 690         printf("Serdes Lane D: ");
 691         if ((current_serdes & MASK_LANE_D) == 0)
 692                 printf("PCIe,\n");
 693         else
 694                 printf("SGMII 2,\n");
 695
 696         printf("SGMII 1 is on lane ");
 697         if ((current_serdes & MASK_SGMII) == 0)
 698                 printf("C.\n");
 699         else
 700                 printf("B.\n");
 701 }
 702
 703 static int serdes_mux_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
 704                           char *const argv[])
 705 {
 706         if (argc != 2)
 707                 return CMD_RET_USAGE;
 708         if (strcmp(argv[1], "sata") == 0) {
 709                 printf("Set serdes lane B to SATA.\n");
 710                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 711         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 712                 printf("Set serdes lane B to SGMII 1.\n");
 713                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 714         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 715                 printf("Set serdes lane C to SGMII 1.\n");
 716                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 717         } else if (strcmp(argv[1], "sgmii2") == 0) {
 718                 printf("Set serdes lane D to SGMII 2.\n");
 719                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 720         } else if (strcmp(argv[1], "pciex1") == 0) {
 721                 printf("Set serdes lane C to PCIe X1.\n");
 722                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 723         } else if (strcmp(argv[1], "pciex2") == 0) {
 724                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 725                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 726         } else if (strcmp(argv[1], "show") == 0) {
 727                 print_serdes_mux();
 728         } else {
 729                 return CMD_RET_USAGE;
 730         }
 731
 732         return 0;
 733 }
 734
 735 U_BOOT_CMD(
 736         lane_bank, 2, 0, serdes_mux_cmd,
 737         "Multiplexed function setting for SerDes Lanes",
 738         "sata\n"
 739         "       -change lane B to sata\n"
 740         "lane_bank sgmii1b\n"
 741         "       -change lane B to SGMII1\n"
 742         "lane_bank sgmii1c\n"
 743         "       -change lane C to SGMII1\n"
 744         "lane_bank sgmii2\n"
 745         "       -change lane D to SGMII2\n"
 746         "lane_bank pciex1\n"
 747         "       -change lane C to PCIeX1\n"
 748         "lane_bank pciex2\n"
 749         "       -change lane C & lane D to PCIeX2\n"
 750         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 751 );
 752 #endif