board/freescale/ls1012aqds/ls1012aqds.c

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/fsl_serdes.h>
  13 #include <asm/arch/fdt.h>
  14 #include <asm/arch/soc.h>
  15 #include <ahci.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <scsi.h>
  19 #include <fm_eth.h>
  20 #include <fsl_csu.h>
  21 #include <fsl_esdhc.h>
  22 #include <fsl_mmdc.h>
  23 #include <spl.h>
  24 #include <netdev.h>
  25
  26 #include "../common/qixis.h"
  27 #include "ls1012aqds_qixis.h"
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  32 {
  33         int timeout = 1000;
  34
  35         out_be32(ptr, value);
  36
  37         while (in_be32(ptr) & bits) {
  38                 udelay(100);
  39                 timeout--;
  40         }
  41         if (timeout <= 0)
  42                 puts("Error: wait for clear timeout.\n");
  43 }
  44
  45 int checkboard(void)
  46 {
  47         char buf[64];
  48         u8 sw;
  49
  50         sw = QIXIS_READ(arch);
  51         printf("Board Arch: V%d, ", sw >> 4);
  52         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  53
  54         sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
  55
  56         if (sw & QIXIS_LBMAP_ALTBANK)
  57                 printf("flash: 2\n");
  58         else
  59                 printf("flash: 1\n");
  60
  61         printf("FPGA: v%d (%s), build %d",
  62                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  63                (int)qixis_read_minor());
  64
  65         /* the timestamp string contains "\n" at the end */
  66         printf(" on %s", qixis_read_time(buf));
  67         return 0;
  68 }
  69
  70 void mmdc_init(void)
  71 {
  72         struct mmdc_p_regs *mmdc =
  73                 (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
  74
  75         out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
  76
  77         /* configure timing parms */
  78         out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
  79         out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
  80         out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
  81         out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
  82
  83         /* other parms  */
  84         out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
  85         out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
  86         out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
  87         out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
  88
  89         /* out of reset delays */
  90         out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
  91
  92         /* physical parms */
  93         out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
  94         out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
  95
  96        /* Enable MMDC */
  97         out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
  98
  99         /* dram init sequence: update MRs */
 100         out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
 101                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
 102         out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
 103                                 CMD_BANK_ADDR_3));
 104         out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
 105                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
 106         out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
 107                                 CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
 108                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
 109
 110        /* dram init sequence: ZQCL */
 111         out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
 112                                 CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
 113         set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
 114                                 CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
 115                                 FORCE_ZQ_AUTO_CALIBRATION);
 116
 117        /* Calibrations now: wr lvl */
 118         out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
 119                                 CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
 120                                 CMD_BANK_ADDR_1));
 121         out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
 122         set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
 123
 124         mdelay(1);
 125
 126         out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
 127                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
 128         out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
 129
 130         mdelay(1);
 131
 132        /* Calibrations now: Read DQS gating calibration */
 133         out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
 134                                 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
 135         out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
 136                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
 137         out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
 138         out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
 139         set_wait_for_bits_clear(&mmdc->mpdgctrl0,
 140                                 AUTO_RD_DQS_GATING_CALIBRATION_EN,
 141                                 AUTO_RD_DQS_GATING_CALIBRATION_EN);
 142
 143         out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
 144                                 CMD_BANK_ADDR_3));
 145
 146        /* Calibrations now: Read calibration */
 147         out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
 148                                 CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
 149         out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
 150                                 CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
 151         out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
 152         set_wait_for_bits_clear(&mmdc->mprddlhwctl,
 153                                 AUTO_RD_CALIBRATION_EN,
 154                                 AUTO_RD_CALIBRATION_EN);
 155
 156         out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
 157                                 CMD_BANK_ADDR_3));
 158
 159        /* PD, SR */
 160         out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
 161         out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
 162
 163        /* refresh scheme */
 164         set_wait_for_bits_clear(&mmdc->mdref,
 165                                 CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
 166                                 START_REFRESH);
 167
 168        /* disable CON_REQ */
 169         out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
 170 }
 171
 172 int dram_init(void)
 173 {
 174         mmdc_init();
 175
 176         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 177
 178         return 0;
 179 }
 180
 181 int board_early_init_f(void)
 182 {
 183         fsl_lsch2_early_init_f();
 184
 185         return 0;
 186 }
 187
 188 #ifdef CONFIG_MISC_INIT_R
 189 int misc_init_r(void)
 190 {
 191         u8 mux_sdhc_cd = 0x80;
 192
 193         i2c_set_bus_num(0);
 194
 195         i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
 196         return 0;
 197 }
 198 #endif
 199
 200 int board_init(void)
 201 {
 202         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
 203                                    CONFIG_SYS_CCI400_ADDR;
 204
 205         /* Set CCI-400 control override register to enable barrier
 206          * transaction */
 207         out_le32(&cci->ctrl_ord,
 208                  CCI400_CTRLORD_EN_BARRIER);
 209
 210 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 211         enable_layerscape_ns_access();
 212 #endif
 213
 214 #ifdef CONFIG_ENV_IS_NOWHERE
 215         gd->env_addr = (ulong)&default_environment[0];
 216 #endif
 217         return 0;
 218 }
 219
 220 int board_eth_init(bd_t *bis)
 221 {
 222         return pci_eth_init(bis);
 223 }
 224
 225 #ifdef CONFIG_OF_BOARD_SETUP
 226 int ft_board_setup(void *blob, bd_t *bd)
 227 {
 228         arch_fixup_fdt(blob);
 229
 230         ft_cpu_setup(blob, bd);
 231
 232         return 0;
 233 }
 234 #endif