board/freescale/ls1012aqds/ls1012aqds.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2021 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <fdt_support.h>
  10 #include <asm/cache.h>
  11 #include <init.h>
  12 #include <asm/global_data.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #ifdef CONFIG_FSL_LS_PPA
  17 #include <asm/arch/ppa.h>
  18 #endif
  19 #include <asm/arch/fdt.h>
  20 #include <asm/arch/mmu.h>
  21 #include <asm/arch/soc.h>
  22 #include <ahci.h>
  23 #include <hwconfig.h>
  24 #include <mmc.h>
  25 #include <env_internal.h>
  26 #include <scsi.h>
  27 #include <fm_eth.h>
  28 #include <fsl_esdhc.h>
  29 #include <fsl_mmdc.h>
  30 #include <spl.h>
  31 #include <netdev.h>
  32 #include "../common/qixis.h"
  33 #include "ls1012aqds_qixis.h"
  34 #include "ls1012aqds_pfe.h"
  35 #include <net/pfe_eth/pfe/pfe_hw.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 int checkboard(void)
  40 {
  41         char buf[64];
  42         u8 sw;
  43
  44         sw = QIXIS_READ(arch);
  45         printf("Board Arch: V%d, ", sw >> 4);
  46         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  47
  48         sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
  49
  50         if (sw & QIXIS_LBMAP_ALTBANK)
  51                 printf("flash: 2\n");
  52         else
  53                 printf("flash: 1\n");
  54
  55         printf("FPGA: v%d (%s), build %d",
  56                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  57                (int)qixis_read_minor());
  58
  59         /* the timestamp string contains "\n" at the end */
  60         printf(" on %s", qixis_read_time(buf));
  61         return 0;
  62 }
  63
  64 #ifdef CONFIG_TFABOOT
  65 int dram_init(void)
  66 {
  67         gd->ram_size = tfa_get_dram_size();
  68         if (!gd->ram_size)
  69                 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  70
  71         return 0;
  72 }
  73 #else
  74 int dram_init(void)
  75 {
  76         static const struct fsl_mmdc_info mparam = {
  77                 0x05180000,     /* mdctl */
  78                 0x00030035,     /* mdpdc */
  79                 0x12554000,     /* mdotc */
  80                 0xbabf7954,     /* mdcfg0 */
  81                 0xdb328f64,     /* mdcfg1 */
  82                 0x01ff00db,     /* mdcfg2 */
  83                 0x00001680,     /* mdmisc */
  84                 0x0f3c8000,     /* mdref */
  85                 0x00002000,     /* mdrwd */
  86                 0x00bf1023,     /* mdor */
  87                 0x0000003f,     /* mdasp */
  88                 0x0000022a,     /* mpodtctrl */
  89                 0xa1390003,     /* mpzqhwctrl */
  90         };
  91
  92         mmdc_init(&mparam);
  93         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  94 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  95         /* This will break-before-make MMU for DDR */
  96         update_early_mmu_table();
  97 #endif
  98
  99         return 0;
 100 }
 101 #endif
 102
 103 int board_early_init_f(void)
 104 {
 105         fsl_lsch2_early_init_f();
 106
 107         return 0;
 108 }
 109
 110 #ifdef CONFIG_MISC_INIT_R
 111 int misc_init_r(void)
 112 {
 113         u8 mux_sdhc_cd = 0x80;
 114         int bus_num = 0;
 115
 116 #if CONFIG_IS_ENABLED(DM_I2C)
 117         struct udevice *dev;
 118         int ret;
 119
 120         ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
 121                                       1, &dev);
 122         if (ret) {
 123                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 124                        bus_num);
 125                 return ret;
 126         }
 127         dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
 128 #else
 129         i2c_set_bus_num(bus_num);
 130
 131         i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
 132 #endif
 133
 134         return 0;
 135 }
 136 #endif
 137
 138 int board_init(void)
 139 {
 140         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 141                                    CONFIG_SYS_CCI400_OFFSET);
 142
 143         /* Set CCI-400 control override register to enable barrier
 144          * transaction */
 145         if (current_el() == 3)
 146                 out_le32(&cci->ctrl_ord,
 147                          CCI400_CTRLORD_EN_BARRIER);
 148
 149 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 150         erratum_a010315();
 151 #endif
 152
 153 #ifdef CONFIG_FSL_LS_PPA
 154         ppa_init();
 155 #endif
 156         return 0;
 157 }
 158
 159 #ifdef CONFIG_FSL_PFE
 160 void board_quiesce_devices(void)
 161 {
 162         pfe_command_stop(0, NULL);
 163 }
 164 #endif
 165
 166 int esdhc_status_fixup(void *blob, const char *compat)
 167 {
 168         char esdhc0_path[] = "/soc/esdhc@1560000";
 169         char esdhc1_path[] = "/soc/esdhc@1580000";
 170         u8 card_id;
 171
 172         do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 173                          sizeof("okay"), 1);
 174
 175         /*
 176          * The Presence Detect 2 register detects the installation
 177          * of cards in various PCI Express or SGMII slots.
 178          *
 179          * STAT_PRS2[7:5]: Specifies the type of card installed in the
 180          * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
 181          */
 182         card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
 183
 184         /* If no adapter is installed in SDHC2, disable SDHC2 */
 185         if (card_id == 0x7)
 186                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 187                                  sizeof("disabled"), 1);
 188         else
 189                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 190                                  sizeof("okay"), 1);
 191         return 0;
 192 }
 193
 194 static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
 195                               char *enet_path, char *mdio_path)
 196 {
 197         do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
 198                          &prop_val.busid, PFE_PROP_LEN, 1);
 199         do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
 200                          &prop_val.phyid, PFE_PROP_LEN, 1);
 201         do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
 202                          &prop_val.mux_val, PFE_PROP_LEN, 1);
 203         do_fixup_by_path(set_blob, enet_path, "phy-mode",
 204                          prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
 205         do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
 206                          &prop_val.phy_mask, PFE_PROP_LEN, 1);
 207         return 0;
 208 }
 209
 210 static void fdt_fsl_fixup_of_pfe(void *blob)
 211 {
 212         int i = 0;
 213         struct pfe_prop_val prop_val;
 214         void *l_blob = blob;
 215
 216         struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
 217         unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
 218                 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
 219         srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 220
 221         for (i = 0; i < NUM_ETH_NODE; i++) {
 222                 switch (srds_s1) {
 223                 case SERDES_1_G_PROTOCOL:
 224                         if (i == 0) {
 225                                 prop_val.busid = cpu_to_fdt32(
 226                                                 ETH_1_1G_BUS_ID);
 227                                 prop_val.phyid = cpu_to_fdt32(
 228                                                 ETH_1_1G_PHY_ID);
 229                                 prop_val.mux_val = cpu_to_fdt32(
 230                                                 ETH_1_1G_MDIO_MUX);
 231                                 prop_val.phy_mask = cpu_to_fdt32(
 232                                                 ETH_1G_MDIO_PHY_MASK);
 233                                 prop_val.phy_mode = "sgmii";
 234                                 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
 235                                                    ETH_1_MDIO);
 236                         } else {
 237                                 prop_val.busid = cpu_to_fdt32(
 238                                                 ETH_2_1G_BUS_ID);
 239                                 prop_val.phyid = cpu_to_fdt32(
 240                                                 ETH_2_1G_PHY_ID);
 241                                 prop_val.mux_val = cpu_to_fdt32(
 242                                                 ETH_2_1G_MDIO_MUX);
 243                                 prop_val.phy_mask = cpu_to_fdt32(
 244                                                 ETH_1G_MDIO_PHY_MASK);
 245                                 prop_val.phy_mode = "rgmii";
 246                                 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
 247                                                    ETH_2_MDIO);
 248                         }
 249                 break;
 250                 case SERDES_2_5_G_PROTOCOL:
 251                         if (i == 0) {
 252                                 prop_val.busid = cpu_to_fdt32(
 253                                                 ETH_1_2_5G_BUS_ID);
 254                                 prop_val.phyid = cpu_to_fdt32(
 255                                                 ETH_1_2_5G_PHY_ID);
 256                                 prop_val.mux_val = cpu_to_fdt32(
 257                                                 ETH_1_2_5G_MDIO_MUX);
 258                                 prop_val.phy_mask = cpu_to_fdt32(
 259                                                 ETH_2_5G_MDIO_PHY_MASK);
 260                                 prop_val.phy_mode = "2500base-x";
 261                                 pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
 262                                                    ETH_1_MDIO);
 263                         } else {
 264                                 prop_val.busid = cpu_to_fdt32(
 265                                                 ETH_2_2_5G_BUS_ID);
 266                                 prop_val.phyid = cpu_to_fdt32(
 267                                                 ETH_2_2_5G_PHY_ID);
 268                                 prop_val.mux_val = cpu_to_fdt32(
 269                                                 ETH_2_2_5G_MDIO_MUX);
 270                                 prop_val.phy_mask = cpu_to_fdt32(
 271                                                 ETH_2_5G_MDIO_PHY_MASK);
 272                                 prop_val.phy_mode = "2500base-x";
 273                                 pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
 274                                                    ETH_2_MDIO);
 275                         }
 276                 break;
 277                 default:
 278                         printf("serdes:[%d]\n", srds_s1);
 279                 }
 280         }
 281 }
 282
 283 #ifdef CONFIG_OF_BOARD_SETUP
 284 int ft_board_setup(void *blob, struct bd_info *bd)
 285 {
 286         arch_fixup_fdt(blob);
 287
 288         ft_cpu_setup(blob, bd);
 289         fdt_fsl_fixup_of_pfe(blob);
 290
 291         return 0;
 292 }
 293 #endif