board/freescale/common/p_corenet/tlb.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/mmu.h>
  28
  29 struct fsl_e_tlb_entry tlb_table[] = {
  30         /* TLB 0 - for temp stack in cache */
  31         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  32                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  33                       MAS3_SW|MAS3_SR, 0,
  34                       0, 0, BOOKE_PAGESZ_4K, 0),
  35         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  36                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  37                       MAS3_SW|MAS3_SR, 0,
  38                       0, 0, BOOKE_PAGESZ_4K, 0),
  39         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  40                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  41                       MAS3_SW|MAS3_SR, 0,
  42                       0, 0, BOOKE_PAGESZ_4K, 0),
  43         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  44                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  45                       MAS3_SW|MAS3_SR, 0,
  46                       0, 0, BOOKE_PAGESZ_4K, 0),
  47 #ifdef CPLD_BASE
  48         SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
  49                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  50                       0, 0, BOOKE_PAGESZ_4K, 0),
  51 #endif
  52
  53 #ifdef PIXIS_BASE
  54         SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
  55                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  56                       0, 0, BOOKE_PAGESZ_4K, 0),
  57 #endif
  58
  59         /* TLB 1 */
  60         /* *I*** - Covers boot page */
  61 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  62         /*
  63          * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  64          * SRAM is at 0xfff00000, it covered the 0xfffff000.
  65          */
  66         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  67                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68                         0, 0, BOOKE_PAGESZ_1M, 1),
  69 #else
  70         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  71                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  72                       0, 0, BOOKE_PAGESZ_4K, 1),
  73 #endif
  74
  75         /* *I*G* - CCSRBAR */
  76         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  77                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  78                       0, 1, BOOKE_PAGESZ_16M, 1),
  79
  80         /* *I*G* - Flash, localbus */
  81         /* This will be changed to *I*G* after relocation to RAM. */
  82         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  83                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  84                       0, 2, BOOKE_PAGESZ_256M, 1),
  85
  86         /* *I*G* - PCI */
  87         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  88                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  89                       0, 3, BOOKE_PAGESZ_1G, 1),
  90
  91         /* *I*G* - PCI */
  92         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  93                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  94                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  95                       0, 4, BOOKE_PAGESZ_256M, 1),
  96
  97         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  98                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  99                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 100                       0, 5, BOOKE_PAGESZ_256M, 1),
 101
 102         /* *I*G* - PCI I/O */
 103         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
 104                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 105                       0, 6, BOOKE_PAGESZ_256K, 1),
 106
 107         /* Bman/Qman */
 108 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
 109         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
 110                       MAS3_SW|MAS3_SR, 0,
 111                       0, 9, BOOKE_PAGESZ_1M, 1),
 112         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
 113                       CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
 114                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 115                       0, 10, BOOKE_PAGESZ_1M, 1),
 116 #endif
 117 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
 118         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
 119                       MAS3_SW|MAS3_SR, 0,
 120                       0, 11, BOOKE_PAGESZ_1M, 1),
 121         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
 122                       CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
 123                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 124                       0, 12, BOOKE_PAGESZ_1M, 1),
 125 #endif
 126 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 127         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 128                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 129                       0, 13, BOOKE_PAGESZ_4M, 1),
 130 #endif
 131 #ifdef CONFIG_SYS_NAND_BASE
 132         /*
 133          * *I*G - NAND
 134          * entry 14 and 15 has been used hard coded, they will be disabled
 135          * in cpu_init_f, so we use entry 16 for nand.
 136          */
 137         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 138                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 139                         0, 16, BOOKE_PAGESZ_1M, 1),
 140 #endif
 141 };
 142
 143 int num_tlb_entries = ARRAY_SIZE(tlb_table);