board/freescale/bsc9131rdb/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <init.h>
   8 #include <vsprintf.h>
   9 #include <asm/mmu.h>
  10 #include <asm/immap_85xx.h>
  11 #include <asm/processor.h>
  12 #include <fsl_ddr_sdram.h>
  13 #include <fsl_ddr_dimm_params.h>
  14 #include <asm/io.h>
  15 #include <asm/fsl_law.h>
  16
  17 #ifndef CONFIG_SYS_DDR_RAW_TIMING
  18 #define CONFIG_SYS_DRAM_SIZE    1024
  19
  20 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
  21         .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  22         .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  23         .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  24         .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
  25         .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
  26         .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
  27         .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
  28         .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  29         .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  30         .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
  31         .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
  32         .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  33         .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
  34         .ddr_data_init = CONFIG_MEM_INIT_VALUE,
  35         .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
  36         .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  37         .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  38         .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  39         .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  40         .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  41         .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
  42         .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  43         .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  44         .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  45 };
  46
  47 fixed_ddr_parm_t fixed_ddr_parm_0[] = {
  48         {750, 850, &ddr_cfg_regs_800},
  49         {0, 0, NULL}
  50 };
  51
  52 unsigned long get_sdram_size(void)
  53 {
  54         return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
  55 }
  56
  57 /*
  58  * Fixed sdram init -- doesn't use serial presence detect.
  59  */
  60 phys_size_t fixed_sdram(void)
  61 {
  62         int i;
  63         char buf[32];
  64         fsl_ddr_cfg_regs_t ddr_cfg_regs;
  65         phys_size_t ddr_size;
  66         ulong ddr_freq, ddr_freq_mhz;
  67
  68         ddr_freq = get_ddr_freq(0);
  69         ddr_freq_mhz = ddr_freq / 1000000;
  70
  71         printf("Configuring DDR for %s MT/s data rate\n",
  72                                 strmhz(buf, ddr_freq));
  73
  74         for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
  75                 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
  76                    (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
  77                         memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
  78                                                         sizeof(ddr_cfg_regs));
  79                         break;
  80                 }
  81         }
  82
  83         if (fixed_ddr_parm_0[i].max_freq == 0) {
  84                 panic("Unsupported DDR data rate %s MT/s data rate\n",
  85                                         strmhz(buf, ddr_freq));
  86         }
  87
  88         ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  89         fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  90
  91         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
  92                                         LAW_TRGT_IF_DDR_1) < 0) {
  93                 printf("ERROR setting Local Access Windows for DDR\n");
  94                 return 0;
  95         }
  96
  97         return ddr_size;
  98 }
  99
 100 #else /* CONFIG_SYS_DDR_RAW_TIMING */
 101 /* Micron MT41J256M8HX-15E */
 102 dimm_params_t ddr_raw_timing = {
 103         .n_ranks = 1,
 104         .rank_density = 1073741824u,
 105         .capacity = 1073741824u,
 106         .primary_sdram_width = 32,
 107         .ec_sdram_width = 0,
 108         .registered_dimm = 0,
 109         .mirrored_dimm = 0,
 110         .n_row_addr = 15,
 111         .n_col_addr = 10,
 112         .n_banks_per_sdram_device = 8,
 113         .edc_config = 0,
 114         .burst_lengths_bitmask = 0x0c,
 115
 116         .tckmin_x_ps = 1870,
 117         .caslat_x = 0x1e << 4,  /* 5,6,7,8 */
 118         .taa_ps = 13125,
 119         .twr_ps = 15000,
 120         .trcd_ps = 13125,
 121         .trrd_ps = 7500,
 122         .trp_ps = 13125,
 123         .tras_ps = 37500,
 124         .trc_ps = 50625,
 125         .trfc_ps = 160000,
 126         .twtr_ps = 7500,
 127         .trtp_ps = 7500,
 128         .refresh_rate_ps = 7800000,
 129         .tfaw_ps = 37500,
 130 };
 131
 132 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 133                 unsigned int controller_number,
 134                 unsigned int dimm_number)
 135 {
 136         const char dimm_model[] = "Fixed DDR on board";
 137
 138         if ((controller_number == 0) && (dimm_number == 0)) {
 139                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 140                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 141                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 142         }
 143
 144         return 0;
 145 }
 146
 147 void fsl_ddr_board_options(memctl_options_t *popts,
 148                                 dimm_params_t *pdimm,
 149                                 unsigned int ctrl_num)
 150 {
 151         int i;
 152         popts->clk_adjust = 6;
 153         popts->cpo_override = 0x1f;
 154         popts->write_data_delay = 2;
 155         popts->half_strength_driver_enable = 1;
 156         /* Write leveling override */
 157         popts->wrlvl_en = 1;
 158         popts->wrlvl_override = 1;
 159         popts->wrlvl_sample = 0xf;
 160         popts->wrlvl_start = 0x8;
 161         popts->trwt_override = 1;
 162         popts->trwt = 0;
 163
 164         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 165                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 166                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 167         }
 168 }
 169
 170 #endif /* CONFIG_SYS_DDR_RAW_TIMING */