board/esd/pmc440/pmc440.c

   1 /*
   2  * (Cg) Copyright 2007-2008
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4  * Based on board/amcc/sequoia/sequoia.c
   5  *
   6  * (C) Copyright 2006
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * (C) Copyright 2006
  10  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15 #include <common.h>
  16 #include <console.h>
  17 #include <libfdt.h>
  18 #include <fdt_support.h>
  19 #include <asm/ppc440.h>
  20 #include <asm/processor.h>
  21 #include <asm/io.h>
  22 #include <asm/bitops.h>
  23 #include <command.h>
  24 #include <i2c.h>
  25 #ifdef CONFIG_RESET_PHY_R
  26 #include <miiphy.h>
  27 #endif
  28 #include <serial.h>
  29 #include <asm/4xx_pci.h>
  30 #include <usb.h>
  31
  32 #include "fpga.h"
  33 #include "pmc440.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  38 extern void __ft_board_setup(void *blob, bd_t *bd);
  39
  40 ulong flash_get_size(ulong base, int banknum);
  41 static int pci_is_66mhz(void);
  42 int is_monarch(void);
  43 static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
  44                                  uchar *buffer, unsigned cnt);
  45
  46 struct serial_device *default_serial_console(void)
  47 {
  48         uchar buf[4];
  49         ulong delay;
  50         int i;
  51         ulong val;
  52
  53         /*
  54          * Use default console on P4 when strapping jumper
  55          * is installed (bootstrap option != 'H').
  56          */
  57         mfsdr(SDR0_PINSTP, val);
  58         if (((val & 0xf0000000) >> 29) != 7)
  59                 return &eserial2_device;
  60
  61         ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
  62         if (!(scratchreg & 0x80)) {
  63                 /* mark scratchreg valid */
  64                 scratchreg = (scratchreg & 0xffffff00) | 0x80;
  65
  66                 i2c_init_all();
  67
  68                 i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
  69                                           0x10, buf, 4);
  70                 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
  71                         scratchreg |= buf[2];
  72
  73                         /* bringup delay for console */
  74                         for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
  75                                 udelay(1000);
  76                 } else
  77                         scratchreg |= 0x01;
  78                 out_be32((void *)GPIO0_ISR3L, scratchreg);
  79         }
  80
  81         if (scratchreg & 0x01)
  82                 return &eserial2_device;
  83         else
  84                 return &eserial1_device;
  85 }
  86
  87 int board_early_init_f(void)
  88 {
  89         u32 sdr0_cust0;
  90         u32 sdr0_pfc1, sdr0_pfc2;
  91         u32 reg;
  92
  93         /* general EBC configuration (disable EBC timeouts) */
  94         mtdcr(EBC0_CFGADDR, EBC0_CFG);
  95         mtdcr(EBC0_CFGDATA, 0xf8400000);
  96
  97         /* Setup the GPIO pins */
  98         out_be32((void *)GPIO0_OR,    0x40000102);
  99         out_be32((void *)GPIO0_TCR,   0x4c90011f);
 100         out_be32((void *)GPIO0_OSRL,  0x28051400);
 101         out_be32((void *)GPIO0_OSRH,  0x55005000);
 102         out_be32((void *)GPIO0_TSRL,  0x08051400);
 103         out_be32((void *)GPIO0_TSRH,  0x55005000);
 104         out_be32((void *)GPIO0_ISR1L, 0x54000000);
 105         out_be32((void *)GPIO0_ISR1H, 0x00000000);
 106         out_be32((void *)GPIO0_ISR2L, 0x44000000);
 107         out_be32((void *)GPIO0_ISR2H, 0x00000100);
 108         out_be32((void *)GPIO0_ISR3L, 0x00000000);
 109         out_be32((void *)GPIO0_ISR3H, 0x00000000);
 110
 111         out_be32((void *)GPIO1_OR,    0x80002408);
 112         out_be32((void *)GPIO1_TCR,   0xd6003c08);
 113         out_be32((void *)GPIO1_OSRL,  0x0a5a0000);
 114         out_be32((void *)GPIO1_OSRH,  0x00000000);
 115         out_be32((void *)GPIO1_TSRL,  0x00000000);
 116         out_be32((void *)GPIO1_TSRH,  0x00000000);
 117         out_be32((void *)GPIO1_ISR1L, 0x00005555);
 118         out_be32((void *)GPIO1_ISR1H, 0x40000000);
 119         out_be32((void *)GPIO1_ISR2L, 0x04010000);
 120         out_be32((void *)GPIO1_ISR2H, 0x00000000);
 121         out_be32((void *)GPIO1_ISR3L, 0x01400000);
 122         out_be32((void *)GPIO1_ISR3H, 0x00000000);
 123
 124         /* patch PLB:PCI divider for 66MHz PCI */
 125         mfcpr(CPR0_SPCID, reg);
 126         if (pci_is_66mhz() && (reg != 0x02000000)) {
 127                 mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
 128
 129                 mfcpr(CPR0_ICFG, reg);
 130                 reg |= CPR0_ICFG_RLI_MASK;
 131                 mtcpr(CPR0_ICFG, reg);
 132
 133                 mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
 134         }
 135
 136         /*
 137          * Setup the interrupt controller polarities, triggers, etc.
 138          */
 139         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 140         mtdcr(UIC0ER, 0x00000000);      /* disable all */
 141         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
 142         mtdcr(UIC0PR, 0xfffff7ef);
 143         mtdcr(UIC0TR, 0x00000000);
 144         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
 145         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 146
 147         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 148         mtdcr(UIC1ER, 0x00000000);      /* disable all */
 149         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
 150         mtdcr(UIC1PR, 0xffffc7f5);
 151         mtdcr(UIC1TR, 0x00000000);
 152         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
 153         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 154
 155         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 156         mtdcr(UIC2ER, 0x00000000);      /* disable all */
 157         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
 158         mtdcr(UIC2PR, 0x27ffffff);
 159         mtdcr(UIC2TR, 0x00000000);
 160         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
 161         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 162
 163         /* select Ethernet pins */
 164         mfsdr(SDR0_PFC1, sdr0_pfc1);
 165         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
 166                 SDR0_PFC1_SELECT_CONFIG_4;
 167         mfsdr(SDR0_PFC2, sdr0_pfc2);
 168         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 169                 SDR0_PFC2_SELECT_CONFIG_4;
 170
 171         /* enable 2nd IIC */
 172         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
 173
 174         mtsdr(SDR0_PFC2, sdr0_pfc2);
 175         mtsdr(SDR0_PFC1, sdr0_pfc1);
 176
 177         /* setup NAND FLASH */
 178         mfsdr(SDR0_CUST0, sdr0_cust0);
 179         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 180                 SDR0_CUST0_NDFC_ENABLE          |
 181                 SDR0_CUST0_NDFC_BW_8_BIT        |
 182                 SDR0_CUST0_NDFC_ARE_MASK        |
 183                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 184         mtsdr(SDR0_CUST0, sdr0_cust0);
 185
 186         return 0;
 187 }
 188
 189 #if defined(CONFIG_MISC_INIT_F)
 190 int misc_init_f(void)
 191 {
 192         struct pci_controller hose;
 193         hose.first_busno = 0;
 194         hose.last_busno = 0;
 195         hose.region_count = 0;
 196
 197         if (getenv("pciearly") && (!is_monarch())) {
 198                 printf("PCI:   early target init\n");
 199                 pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
 200                 pci_target_init(&hose);
 201         }
 202         return 0;
 203 }
 204 #endif
 205
 206 /*
 207  * misc_init_r.
 208  */
 209 int misc_init_r(void)
 210 {
 211         uint pbcr;
 212         int size_val = 0;
 213         u32 reg;
 214         unsigned long usb2d0cr = 0;
 215         unsigned long usb2phy0cr, usb2h0cr = 0;
 216         unsigned long sdr0_pfc1;
 217         unsigned long sdr0_srst0, sdr0_srst1;
 218         char *act = getenv("usbact");
 219
 220         /*
 221          * FLASH stuff...
 222          */
 223
 224         /* Re-do sizing to get full correct info */
 225
 226         /* adjust flash start and offset */
 227         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 228         gd->bd->bi_flashoffset = 0;
 229
 230         mtdcr(EBC0_CFGADDR, PB0CR);
 231         pbcr = mfdcr(EBC0_CFGDATA);
 232         size_val = ffs(gd->bd->bi_flashsize) - 21;
 233         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 234         mtdcr(EBC0_CFGADDR, PB0CR);
 235         mtdcr(EBC0_CFGDATA, pbcr);
 236
 237         /*
 238          * Re-check to get correct base address
 239          */
 240         flash_get_size(gd->bd->bi_flashstart, 0);
 241
 242 #ifdef CONFIG_ENV_IS_IN_FLASH
 243         /* Monitor protection ON by default */
 244         (void)flash_protect(FLAG_PROTECT_SET,
 245                             -CONFIG_SYS_MONITOR_LEN,
 246                             0xffffffff,
 247                             &flash_info[0]);
 248
 249         /* Env protection ON by default */
 250         (void)flash_protect(FLAG_PROTECT_SET,
 251                             CONFIG_ENV_ADDR_REDUND,
 252                             CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
 253                             &flash_info[0]);
 254 #endif
 255
 256         /*
 257          * USB suff...
 258          */
 259         if ((act == NULL || strcmp(act, "host") == 0) &&
 260             !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 261                 /* SDR Setting */
 262                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 263                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 264                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 265                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 266
 267                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 268                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 269                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 270                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
 271                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 272                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 273                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 274                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 275                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 276                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 277
 278                 /*
 279                  * An 8-bit/60MHz interface is the only possible alternative
 280                  * when connecting the Device to the PHY
 281                  */
 282                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 283                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
 284
 285                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 286                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 287
 288                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 289                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 290                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 291                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 292
 293                 /*
 294                  * Take USB out of reset:
 295                  * -Initial status = all cores are in reset
 296                  * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
 297                  * -wait 1 ms
 298                  * -deassert reset to PHY
 299                  * -wait 1 ms
 300                  * -deassert  reset to HOST
 301                  * -wait 4 ms
 302                  * -deassert all other resets
 303                  */
 304                 mfsdr(SDR0_SRST1, sdr0_srst1);
 305                 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |      \
 306                                 SDR0_SRST1_P4OPB0 |     \
 307                                 SDR0_SRST1_OPBA2 |      \
 308                                 SDR0_SRST1_PLB42OPB1 |  \
 309                                 SDR0_SRST1_OPB2PLB40);
 310                 mtsdr(SDR0_SRST1, sdr0_srst1);
 311                 udelay(1000);
 312
 313                 mfsdr(SDR0_SRST1, sdr0_srst1);
 314                 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
 315                 mtsdr(SDR0_SRST1, sdr0_srst1);
 316                 udelay(1000);
 317
 318                 mfsdr(SDR0_SRST0, sdr0_srst0);
 319                 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
 320                 mtsdr(SDR0_SRST0, sdr0_srst0);
 321                 udelay(4000);
 322
 323                 /* finally all the other resets */
 324                 mtsdr(SDR0_SRST1, 0x00000000);
 325                 mtsdr(SDR0_SRST0, 0x00000000);
 326
 327                 if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 328                         /* enable power on USB socket */
 329                         out_be32((void *)GPIO1_OR,
 330                                  in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
 331                 }
 332
 333                 printf("USB:   Host\n");
 334
 335         } else if ((strcmp(act, "dev") == 0) ||
 336                    (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
 337                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 338
 339                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 340                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 341                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 342                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 343                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 344                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 345                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 346                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 347                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 348
 349                 udelay (1000);
 350                 mtsdr(SDR0_SRST1, 0x672c6000);
 351
 352                 udelay (1000);
 353                 mtsdr(SDR0_SRST0, 0x00000080);
 354
 355                 udelay (1000);
 356                 mtsdr(SDR0_SRST1, 0x60206000);
 357
 358                 *(unsigned int *)(0xe0000350) = 0x00000001;
 359
 360                 udelay (1000);
 361                 mtsdr(SDR0_SRST1, 0x60306000);
 362
 363                 /* SDR Setting */
 364                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 365                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 366                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 367                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 368
 369                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 370                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 371                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 372                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
 373                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 374                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
 375                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 376                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
 377                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 378                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
 379
 380                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 381                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
 382
 383                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 384
 385                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 386                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
 387
 388                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 389                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 390                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 391                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 392
 393                 /*clear resets*/
 394                 udelay(1000);
 395                 mtsdr(SDR0_SRST1, 0x00000000);
 396                 udelay(1000);
 397                 mtsdr(SDR0_SRST0, 0x00000000);
 398
 399                 printf("USB:   Device\n");
 400         }
 401
 402         /*
 403          * Clear PLB4A0_ACR[WRP]
 404          * This fix will make the MAL burst disabling patch for the Linux
 405          * EMAC driver obsolete.
 406          */
 407         reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
 408         mtdcr(PLB4A0_ACR, reg);
 409
 410 #ifdef CONFIG_FPGA
 411         pmc440_init_fpga();
 412 #endif
 413
 414         /* turn off POST LED */
 415         out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
 416         /* turn on RUN LED */
 417         out_be32((void *)GPIO0_OR,
 418                  in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N);
 419         return 0;
 420 }
 421
 422 int is_monarch(void)
 423 {
 424         if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH)
 425                 return 0;
 426
 427         return 1;
 428 }
 429
 430 static int pci_is_66mhz(void)
 431 {
 432         if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN)
 433                 return 1;
 434         return 0;
 435 }
 436
 437 static int board_revision(void)
 438 {
 439         return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
 440 }
 441
 442 int checkboard(void)
 443 {
 444         puts("Board: esd GmbH - PMC440");
 445
 446         gd->board_type = board_revision();
 447         printf(", Rev 1.%ld, ", gd->board_type);
 448
 449         if (!is_monarch()) {
 450                 puts("non-");
 451         }
 452
 453         printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
 454         return (0);
 455 }
 456
 457
 458 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 459 /*
 460  * Assign interrupts to PCI devices. Some OSs rely on this.
 461  */
 462 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 463 {
 464         unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
 465
 466         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
 467                                    int_line[PCI_DEV(dev) & 0x03]);
 468 }
 469 #endif
 470
 471 /*
 472  * pci_target_init
 473  *
 474  * The bootstrap configuration provides default settings for the pci
 475  * inbound map (PIM). But the bootstrap config choices are limited and
 476  * may not be sufficient for a given board.
 477  */
 478 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 479 void pci_target_init(struct pci_controller *hose)
 480 {
 481         char *ptmla_str, *ptmms_str;
 482
 483         /*
 484          * Set up Direct MMIO registers
 485          */
 486         /*
 487          * PowerPC440EPX PCI Master configuration.
 488          * Map one 1Gig range of PLB/processor addresses to PCI memory space.
 489          * PLB address 0x80000000-0xBFFFFFFF
 490          *     ==> PCI address 0x80000000-0xBFFFFFFF
 491          * Use byte reversed out routines to handle endianess.
 492          * Make this region non-prefetchable.
 493          */
 494         out32r(PCIL0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute */
 495                                                 /* - disabled b4 setting */
 496         out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
 497         out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */
 498         out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 499         out32r(PCIL0_PMM0MA, 0xc0000001);       /* 1G + No prefetching, */
 500                                                 /* and enable region */
 501
 502         if (!is_monarch()) {
 503                 ptmla_str = getenv("ptm1la");
 504                 ptmms_str = getenv("ptm1ms");
 505                 if(NULL != ptmla_str && NULL != ptmms_str ) {
 506                         out32r(PCIL0_PTM1MS,
 507                                simple_strtoul(ptmms_str, NULL, 16));
 508                         out32r(PCIL0_PTM1LA,
 509                                simple_strtoul(ptmla_str, NULL, 16));
 510                 } else {
 511                         /* BAR1: default top 64MB of RAM */
 512                         out32r(PCIL0_PTM1MS, 0xfc000001);
 513                         out32r(PCIL0_PTM1LA, 0x0c000000);
 514                 }
 515         } else {
 516                 /* BAR1: default: complete 256MB RAM */
 517                 out32r(PCIL0_PTM1MS, 0xf0000001);
 518                 out32r(PCIL0_PTM1LA, 0x00000000);
 519         }
 520
 521         ptmla_str = getenv("ptm2la");           /* Local Addr. Reg */
 522         ptmms_str = getenv("ptm2ms");           /* Memory Size/Attribute */
 523         if(NULL != ptmla_str && NULL != ptmms_str ) {
 524                 out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
 525                 out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
 526         } else {
 527                 /* BAR2: default: 4MB FPGA */
 528                 out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
 529                 out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
 530         }
 531
 532         if (is_monarch()) {
 533                 /* BAR2: map FPGA registers behind system memory at 1GB */
 534                 pci_hose_write_config_dword(hose, 0,
 535                                             PCI_BASE_ADDRESS_2, 0x40000008);
 536         }
 537
 538         /*
 539          * Set up Configuration registers
 540          */
 541
 542         /* Program the board's vendor id */
 543         pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
 544                                    CONFIG_SYS_PCI_SUBSYS_VENDORID);
 545
 546         /* disabled for PMC405 backward compatibility */
 547         /* Configure command register as bus master */
 548         /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
 549
 550
 551         /* 240nS PCI clock */
 552         pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
 553
 554         /* No error reporting */
 555         pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
 556
 557         if (!is_monarch()) {
 558                 /* Program the board's subsystem id/classcode */
 559                 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
 560                                            CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
 561                 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
 562                                            CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
 563
 564                 /* PCI configuration done: release ERREADY */
 565                 out_be32((void *)GPIO1_OR,
 566                          in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY);
 567                 out_be32((void *)GPIO1_TCR,
 568                          in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY);
 569         } else {
 570                 /* Program the board's subsystem id/classcode */
 571                 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
 572                                            CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
 573                 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
 574                                            CONFIG_SYS_PCI_CLASSCODE_MONARCH);
 575         }
 576
 577         /* enable host configuration */
 578         pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
 579 }
 580 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 581
 582 /*
 583  * Override weak default pci_master_init()
 584  */
 585 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 586 void pci_master_init(struct pci_controller *hose)
 587 {
 588         /*
 589          * Only configure the master in monach mode
 590          */
 591         if (is_monarch())
 592                 __pci_master_init(hose);
 593 }
 594 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 595
 596 static void wait_for_pci_ready(void)
 597 {
 598         if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) {
 599                 printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
 600                 while (1) {
 601                         if (ctrlc()) {
 602                                 puts("abort\n");
 603                                 break;
 604                         }
 605                         if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) {
 606                                 printf("done\n");
 607                                 break;
 608                         }
 609                 }
 610         }
 611 }
 612
 613 /*
 614  * Override weak is_pci_host()
 615  *
 616  * This routine is called to determine if a pci scan should be
 617  * performed. With various hardware environments (especially cPCI and
 618  * PPMC) it's insufficient to depend on the state of the arbiter enable
 619  * bit in the strap register, or generic host/adapter assumptions.
 620  *
 621  * Rather than hard-code a bad assumption in the general 440 code, the
 622  * 440 pci code requires the board to decide at runtime.
 623  *
 624  * Return 0 for adapter mode, non-zero for host (monarch) mode.
 625  */
 626 #if defined(CONFIG_PCI)
 627 int is_pci_host(struct pci_controller *hose)
 628 {
 629         char *s = getenv("pciscan");
 630         if (s == NULL)
 631                 if (is_monarch()) {
 632                         wait_for_pci_ready();
 633                         return 1;
 634                 } else
 635                         return 0;
 636         else if (!strcmp(s, "yes"))
 637                 return 1;
 638
 639         return 0;
 640 }
 641 #endif /* defined(CONFIG_PCI) */
 642
 643 #ifdef CONFIG_RESET_PHY_R
 644 static int pmc440_setup_vsc8601(char *devname, int phy_addr,
 645                                 unsigned short behavior, unsigned short method)
 646 {
 647         /* adjust LED behavior */
 648         if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) {
 649                 printf("Phy%d: register write access failed\n", phy_addr);
 650                 return -1;
 651         }
 652
 653         miiphy_write(devname, phy_addr, 0x11, 0x0010);
 654         miiphy_write(devname, phy_addr, 0x11, behavior);
 655         miiphy_write(devname, phy_addr, 0x10, method);
 656         miiphy_write(devname, phy_addr, 0x1f, 0x0000);
 657
 658         return 0;
 659 }
 660
 661 static int pmc440_setup_ksz9031(char *devname, int phy_addr)
 662 {
 663         unsigned short id1, id2;
 664
 665         if (miiphy_read(devname, phy_addr, 2, &id1) ||
 666             miiphy_read(devname, phy_addr, 3, &id2)) {
 667                 printf("Phy%d: cannot read id\n", phy_addr);
 668                 return -1;
 669         }
 670
 671         if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) {
 672                 printf("Phy%d: unexpected id\n", phy_addr);
 673                 return -1;
 674         }
 675
 676         /* MMD 2.08: adjust tx_clk pad skew */
 677         miiphy_write(devname, phy_addr, 0x0d, 2);
 678         miiphy_write(devname, phy_addr, 0x0e, 8);
 679         miiphy_write(devname, phy_addr, 0x0d, 0x4002);
 680         miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5));
 681
 682         return 0;
 683 }
 684
 685 void reset_phy(void)
 686 {
 687         char *s;
 688         unsigned short val_method, val_behavior;
 689
 690         if (gd->board_type < 4) {
 691                 /* special LED setup for NGCC/CANDES */
 692                 s = getenv("bd_type");
 693                 if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
 694                         val_method   = 0x0e0a;
 695                         val_behavior = 0x0cf2;
 696                 } else {
 697                         /* PMC440 standard type */
 698                         val_method   = 0x0e10;
 699                         val_behavior = 0x0cf0;
 700                 }
 701
 702                 /* boards up to rev. 1.3 use Vitesse VSC8601 phys */
 703                 pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR,
 704                                      val_method, val_behavior);
 705                 pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR,
 706                                      val_method, val_behavior);
 707         } else {
 708                 /* rev. 1.4 uses a Micrel KSZ9031 */
 709                 pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR);
 710                 pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR);
 711         }
 712 }
 713 #endif
 714
 715 #if defined(CONFIG_SYS_EEPROM_WREN)
 716 /*
 717  *  Input: <dev_addr> I2C address of EEPROM device to enable.
 718  *         <state>    -1: deliver current state
 719  *                     0: disable write
 720  *                     1: enable write
 721  *  Returns:          -1: wrong device address
 722  *                     0: dis-/en- able done
 723  *                   0/1: current state if <state> was -1.
 724  */
 725 int eeprom_write_enable(unsigned dev_addr, int state)
 726 {
 727         if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
 728             (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
 729                 return -1;
 730         } else {
 731                 switch (state) {
 732                 case 1:
 733                         /* Enable write access, clear bit GPIO_SINT2. */
 734                         out_be32((void *)GPIO0_OR,
 735                               in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
 736                         state = 0;
 737                         break;
 738                 case 0:
 739                         /* Disable write access, set bit GPIO_SINT2. */
 740                         out_be32((void *)GPIO0_OR,
 741                                  in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
 742                         state = 0;
 743                         break;
 744                 default:
 745                         /* Read current status back. */
 746                         state = (0 == (in_be32((void *)GPIO0_OR)
 747                                        & GPIO0_EP_EEP));
 748                         break;
 749                 }
 750         }
 751         return state;
 752 }
 753 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 754
 755 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
 756 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
 757                            uchar *buffer, unsigned cnt)
 758 {
 759         unsigned end = offset + cnt;
 760         unsigned blk_off;
 761         int rcode = 0;
 762
 763 #if defined(CONFIG_SYS_EEPROM_WREN)
 764         eeprom_write_enable(dev_addr, 1);
 765 #endif
 766         /*
 767          * Write data until done or would cross a write page boundary.
 768          * We must write the address again when changing pages
 769          * because the address counter only increments within a page.
 770          */
 771         while (offset < end) {
 772                 unsigned alen, len;
 773                 unsigned maxlen;
 774                 uchar addr[2];
 775
 776                 blk_off = offset & 0xFF;        /* block offset */
 777
 778                 addr[0] = offset >> 8;          /* block number */
 779                 addr[1] = blk_off;              /* block offset */
 780                 alen    = 2;
 781                 addr[0] |= dev_addr;            /* insert device address */
 782
 783                 len = end - offset;
 784
 785 #define BOOT_EEPROM_PAGE_SIZE      (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
 786 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
 787
 788                 maxlen = BOOT_EEPROM_PAGE_SIZE -
 789                         BOOT_EEPROM_PAGE_OFFSET(blk_off);
 790                 if (maxlen > I2C_RXTX_LEN)
 791                         maxlen = I2C_RXTX_LEN;
 792
 793                 if (len > maxlen)
 794                         len = maxlen;
 795
 796                 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
 797                         rcode = 1;
 798
 799                 buffer += len;
 800                 offset += len;
 801
 802 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
 803                 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 804 #endif
 805         }
 806 #if defined(CONFIG_SYS_EEPROM_WREN)
 807         eeprom_write_enable(dev_addr, 0);
 808 #endif
 809         return rcode;
 810 }
 811
 812 static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
 813                                  uchar *buffer, unsigned cnt)
 814 {
 815         unsigned end = offset + cnt;
 816         unsigned blk_off;
 817         int rcode = 0;
 818
 819         /*
 820          * Read data until done or would cross a page boundary.
 821          * We must write the address again when changing pages
 822          * because the next page may be in a different device.
 823          */
 824         while (offset < end) {
 825                 unsigned alen, len;
 826                 unsigned maxlen;
 827                 uchar addr[2];
 828
 829                 blk_off = offset & 0xFF;        /* block offset */
 830
 831                 addr[0] = offset >> 8;          /* block number */
 832                 addr[1] = blk_off;              /* block offset */
 833                 alen    = 2;
 834
 835                 addr[0] |= dev_addr;            /* insert device address */
 836
 837                 len = end - offset;
 838
 839                 maxlen = 0x100 - blk_off;
 840                 if (maxlen > I2C_RXTX_LEN)
 841                         maxlen = I2C_RXTX_LEN;
 842                 if (len > maxlen)
 843                         len = maxlen;
 844
 845                 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
 846                         rcode = 1;
 847                 buffer += len;
 848                 offset += len;
 849         }
 850
 851         return rcode;
 852 }
 853
 854 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 855 int board_usb_init(int index, enum usb_init_type init)
 856 {
 857         char *act = getenv("usbact");
 858         int i;
 859
 860         if ((act == NULL || strcmp(act, "host") == 0) &&
 861             !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT))
 862                 /* enable power on USB socket */
 863                 out_be32((void *)GPIO1_OR,
 864                          in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
 865
 866         for (i=0; i<1000; i++)
 867                 udelay(1000);
 868
 869         return 0;
 870 }
 871
 872 int usb_board_stop(void)
 873 {
 874         /* disable power on USB socket */
 875         out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N);
 876         return 0;
 877 }
 878
 879 int board_usb_cleanup(int index, enum usb_init_type init)
 880 {
 881         return usb_board_stop();
 882 }
 883 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
 884
 885 #ifdef CONFIG_OF_BOARD_SETUP
 886 int ft_board_setup(void *blob, bd_t *bd)
 887 {
 888         int rc;
 889
 890         __ft_board_setup(blob, bd);
 891
 892         /*
 893          * Disable PCI in non-monarch mode.
 894          */
 895         if (!is_monarch()) {
 896                 rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
 897                                           "disabled", sizeof("disabled"), 1);
 898                 if (rc) {
 899                         printf("Unable to update property status in PCI node, ");
 900                         printf("err=%s\n", fdt_strerror(rc));
 901                 }
 902         }
 903
 904         return 0;
 905 }
 906 #endif /* CONFIG_OF_BOARD_SETUP */