board/ccv/xpress/spl.c

   1 /*
   2  * SPL specific code for CCV xPress
   3  *
   4  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <spl.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/mx6-ddr.h>
  13 #include <asm/arch/crm_regs.h>
  14
  15 /* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */
  16
  17 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  18         .grp_addds = 0x00000030,
  19         .grp_ddrmode_ctl = 0x00020000,
  20         .grp_b0ds = 0x00000030,
  21         .grp_ctlds = 0x00000030,
  22         .grp_b1ds = 0x00000030,
  23         .grp_ddrpke = 0x00000000,
  24         .grp_ddrmode = 0x00020000,
  25         .grp_ddr_type = 0x000c0000,
  26 };
  27
  28 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  29         .dram_dqm0 = 0x00000030,
  30         .dram_dqm1 = 0x00000030,
  31         .dram_ras = 0x00000030,
  32         .dram_cas = 0x00000030,
  33         .dram_odt0 = 0x00000030,
  34         .dram_odt1 = 0x00000030,
  35         .dram_sdba2 = 0x00000000,
  36         .dram_sdclk_0 = 0x00000008,
  37         .dram_sdqs0 = 0x00000038,
  38         .dram_sdqs1 = 0x00000030,
  39         .dram_reset = 0x00000030,
  40 };
  41
  42 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  43         .p0_mpwldectrl0 = 0x00000000,
  44         .p0_mpdgctrl0 = 0x4164015C,
  45         .p0_mprddlctl = 0x40404446,
  46         .p0_mpwrdlctl = 0x40405A52,
  47 };
  48
  49 struct mx6_ddr_sysinfo ddr_sysinfo = {
  50         .dsize = 0,
  51         .cs_density = 20,
  52         .ncs = 1,
  53         .cs1_mirror = 0,
  54         .rtt_wr = 2,
  55         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
  56         .walat = 1,             /* Write additional latency */
  57         .ralat = 5,             /* Read additional latency */
  58         .mif3_mode = 3,         /* Command prediction working mode */
  59         .bi_on = 1,             /* Bank interleaving enabled */
  60         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
  61         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
  62         .ddr_type = DDR_TYPE_DDR3,
  63         .refsel = 1,            /* Refresh cycles at 32KHz */
  64         .refr = 7,              /* 8 refresh commands per refresh cycle */
  65 };
  66
  67 static struct mx6_ddr3_cfg mem_ddr = {
  68         .mem_speed = 800,
  69         .density = 4,
  70         .width = 16,
  71         .banks = 8,
  72         .rowaddr = 13,
  73         .coladdr = 10,
  74         .pagesz = 2,
  75         .trcd = 1375,
  76         .trcmin = 4875,
  77         .trasmin = 3500,
  78 };
  79
  80 static void ccgr_init(void)
  81 {
  82         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  83
  84         writel(0xFFFFFFFF, &ccm->CCGR0);
  85         writel(0xFFFFFFFF, &ccm->CCGR1);
  86         writel(0xFFFFFFFF, &ccm->CCGR2);
  87         writel(0xFFFFFFFF, &ccm->CCGR3);
  88         writel(0xFFFFFFFF, &ccm->CCGR4);
  89         writel(0xFFFFFFFF, &ccm->CCGR5);
  90         writel(0xFFFFFFFF, &ccm->CCGR6);
  91         writel(0xFFFFFFFF, &ccm->CCGR7);
  92 }
  93
  94 static void spl_dram_init(void)
  95 {
  96         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  97         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  98 }
  99
 100 void board_init_f(ulong dummy)
 101 {
 102         /* Setup AIPS and disable watchdog */
 103         arch_cpu_init();
 104
 105         ccgr_init();
 106
 107         /* Setup iomux and i2c */
 108         board_early_init_f();
 109
 110         /* Setup GP timer */
 111         timer_init();
 112
 113         /* UART clocks enabled and gd valid - init serial console */
 114         preloader_console_init();
 115
 116         /* DDR initialization */
 117         spl_dram_init();
 118 }