board/atmel/sama5d4_xplained/sama5d4_xplained.c

   1 /*
   2  * Copyright (C) 2014 Atmel
   3  *                    Bo Shen <voice.shen@atmel.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/at91_common.h>
  11 #include <asm/arch/at91_rstc.h>
  12 #include <asm/arch/atmel_mpddrc.h>
  13 #include <asm/arch/gpio.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/sama5d3_smc.h>
  16 #include <asm/arch/sama5d4.h>
  17 #include <debug_uart.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #ifdef CONFIG_NAND_ATMEL
  22 static void sama5d4_xplained_nand_hw_init(void)
  23 {
  24         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  25
  26         at91_periph_clk_enable(ATMEL_ID_SMC);
  27
  28         /* Configure SMC CS3 for NAND */
  29         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  30                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  31                &smc->cs[3].setup);
  32         writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
  33                AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  34                &smc->cs[3].pulse);
  35         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  36                &smc->cs[3].cycle);
  37         writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  38                AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
  39                AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  40                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  41         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  42                AT91_SMC_MODE_EXNW_DISABLE |
  43                AT91_SMC_MODE_DBW_8 |
  44                AT91_SMC_MODE_TDF_CYCLE(3),
  45                &smc->cs[3].mode);
  46
  47         at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);   /* D0 */
  48         at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);   /* D1 */
  49         at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);   /* D2 */
  50         at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);   /* D3 */
  51         at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);   /* D4 */
  52         at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);  /* D5 */
  53         at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);  /* D6 */
  54         at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);  /* D7 */
  55         at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);  /* RE */
  56         at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);  /* WE */
  57         at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);  /* NCS */
  58         at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);  /* RDY */
  59         at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);  /* ALE */
  60         at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);  /* CLE */
  61 }
  62 #endif
  63
  64 #ifdef CONFIG_CMD_USB
  65 static void sama5d4_xplained_usb_hw_init(void)
  66 {
  67         at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
  68         at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
  69 }
  70 #endif
  71
  72 #ifdef CONFIG_BOARD_LATE_INIT
  73 int board_late_init(void)
  74 {
  75 #ifdef CONFIG_DM_VIDEO
  76         at91_video_show_board_info();
  77 #endif
  78         return 0;
  79 }
  80 #endif
  81
  82 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  83 static void sama5d4_xplained_serial3_hw_init(void)
  84 {
  85         at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);  /* TXD3 */
  86         at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);  /* RXD3 */
  87
  88         /* Enable clock */
  89         at91_periph_clk_enable(ATMEL_ID_USART3);
  90 }
  91
  92 void board_debug_uart_init(void)
  93 {
  94         sama5d4_xplained_serial3_hw_init();
  95 }
  96 #endif
  97
  98 #ifdef CONFIG_BOARD_EARLY_INIT_F
  99 int board_early_init_f(void)
 100 {
 101 #ifdef CONFIG_DEBUG_UART
 102         debug_uart_init();
 103 #endif
 104         return 0;
 105 }
 106 #endif
 107
 108 #define AT24MAC_MAC_OFFSET      0x9a
 109
 110 #ifdef CONFIG_MISC_INIT_R
 111 int misc_init_r(void)
 112 {
 113 #ifdef CONFIG_I2C_EEPROM
 114         at91_set_ethaddr(AT24MAC_MAC_OFFSET);
 115 #endif
 116         return 0;
 117 }
 118 #endif
 119
 120 int board_init(void)
 121 {
 122         /* adress of boot parameters */
 123         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 124
 125 #ifdef CONFIG_NAND_ATMEL
 126         sama5d4_xplained_nand_hw_init();
 127 #endif
 128 #ifdef CONFIG_CMD_USB
 129         sama5d4_xplained_usb_hw_init();
 130 #endif
 131
 132         return 0;
 133 }
 134
 135 int dram_init(void)
 136 {
 137         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 138                                     CONFIG_SYS_SDRAM_SIZE);
 139         return 0;
 140 }
 141
 142 /* SPL */
 143 #ifdef CONFIG_SPL_BUILD
 144 void spl_board_init(void)
 145 {
 146 #if CONFIG_NAND_BOOT
 147         sama5d4_xplained_nand_hw_init();
 148 #endif
 149 }
 150
 151 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 152 {
 153         ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 154
 155         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 156                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 157                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 158                     ATMEL_MPDDRC_CR_NB_8BANKS |
 159                     ATMEL_MPDDRC_CR_NDQS_DISABLED |
 160                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 161                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 162
 163         ddr2->rtr = 0x2b0;
 164
 165         ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 166                       3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 167                       3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 168                       10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 169                       3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 170                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 171                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 172                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 173
 174         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 175                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 176                       25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 177                       23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 178
 179         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 180                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 181                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 182                       2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 183                       8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 184 }
 185
 186 void mem_init(void)
 187 {
 188         struct atmel_mpddrc_config ddr2;
 189
 190         ddr2_conf(&ddr2);
 191
 192         /* Enable MPDDR clock */
 193         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 194         at91_system_clk_enable(AT91_PMC_DDR);
 195
 196         /* DDRAM2 Controller initialize */
 197         ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 198 }
 199
 200 void at91_pmc_init(void)
 201 {
 202         u32 tmp;
 203
 204         tmp = AT91_PMC_PLLAR_29 |
 205               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 206               AT91_PMC_PLLXR_MUL(87) |
 207               AT91_PMC_PLLXR_DIV(1);
 208         at91_plla_init(tmp);
 209
 210         at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
 211
 212         tmp = AT91_PMC_MCKR_H32MXDIV |
 213               AT91_PMC_MCKR_PLLADIV_2 |
 214               AT91_PMC_MCKR_MDIV_3 |
 215               AT91_PMC_MCKR_CSS_PLLA;
 216         at91_mck_init(tmp);
 217 }
 218 #endif